Contents (up to the 2nd level)

Core list items

The framework contain 3 basic parts:

  1. core module, which handle ioctl calls and interact with driver.
  2. Various bus glue (now it is obio(mem), mii(MDIO) and IIC in near future)
  3. drivers. Atheros AR8x16, Broadcom BCM53xx, Ralink RT305xF, Realtek RTL8305/09
  4. FloatPHY, pseudo driver which find master switchX device and ask his PHY reg's.
  5. switchctl utility.

Descriptions

switchctl

Currently can do

switchctl /dev/switch0 (get|set) (reg|port|vlan) [flags]

get/set port: get or set port flags:

Example:

switchctl /dev/switch0 set port 2 pvid 2 flags IngressCheck LAN Tagged

get/set vlan V:

Example:

switchctl /dev/switch0 set vlan 2 vid 12
switchctl /dev/switch0 set vlan 2 add 2 u
switchctl /dev/switch0 set vlan 2 del 1

get/set reg: Generic access to registers. Have 2 address modifiers:

Example:

# switchctl /dev/switch0 get reg 0x80000008
Reg 0x80000008 Value = 0x012603e2
# switchctl /dev/switch0 get reg 0x00000008
Reg 0x00000008 Value = 0x0000ffff
# switchctl /dev/switch0 get reg 0x40000001
Reg 0x40000001 Value = 0x00007949
# switchctl /dev/switch0 set reg 0x80000008 0x012603e2
Reg 0x80000008 Value = 0x012603e2 (Old value = 0x012603e2)

FloatPHY

pseudo driver which attach to miibus like normal PHY, but do find master switchX device and ask his PHY reg's. Main problem with that driver - is usage of newbus calls between independent device (not a parent <-> child), since floatphyX query set/get methods of switchX.

Use hints:

Switch Framework Internals

I will describe as example 4 situation that current framework is cover:

  1. Ralink RT305X SoC, internal switch, one NIC with two paths.
  2. Atheros AR7240 SoC, two NIC, but MDIO routed only from second
  3. Cavium Octeon CN5010, one NIC with three paths + BCM53115 switch + some Broadcom PHY

Ralink RT305X - is simple one Attached by obio0 if driver present in kernel.

VLAN features: it have so called global untagged flag, so port can be member of any VLAN but may be tagged or untagged in all VLAN in same time.

How to enable: just add following into kernel config file.

#------------------------------------------------
device switch
device switch_rt305x
#------------------------------------------------

Atheros AR7240

Atheros AR7240 - very interesting. have AR8216 internal switch and two arge NICs.

arge0 MII bus connected to PHY4 which configured as separate PHY(not attached to switch core). But PHY4 reg's can be accessible only via switch MDIO bus access. arge1 MII bus connected to switch MII. But MDIO bus wired only on arge0, so if arge0 want to know speed and link status, it must ask switch connected to miibus attached to arge1. [1] Page 3

VLAN features: Like RT395x use global untagged like flag.

How to enable (example config for AR7240 in patch)

Config:

#------------------------------------------------
device          mii
device          switch
device          switch_ar8x16
#------------------------------------------------

hints:

#------------------------------------------------
# No probe at all
# First MDIO connected to switch which not have real PHY regs
hint.miibus.0.phymask="0x00000000"
# Second MDIO not wired at all
hint.miibus.1.phymask="0x00000000"

# Connect pseudo PHY driver to miibus0
hint.floatphy.0.at="miibus0"
hint.floatphy.0.phyno=0
# floatphy0 will ask switch0
hint.floatphy.0.master="switch"
hint.floatphy.0.master_unit=0
# and get link status from PHYs masked by 0x00000010
hint.floatphy.0.master_phys=0x00000010 # Sense PHY4
hint.floatphy.0.flags=0x00000000
# Default link speed 100 (if no access to master)
hint.floatphy.0.speed=100

# Switch attached to MDIO bus on arge0
hint.switch.0.at="miibus0"
hint.switch.0.phyno=1
# AR8x16 Magic register which can configure PHY4 as a standalone PHY
hint.ar8x16_switch.0.mii_mode=0x012603e2

hint.floatphy.1.at="miibus1"
hint.floatphy.1.phyno=0
hint.floatphy.1.master="switch"
hint.floatphy.1.master_unit=0
# check link on PHY0-PHY3 (link on any rise link on arge1)
hint.floatphy.1.master_phys=0x0000000f # Link Sensing PHY0-PHY3
hint.floatphy.1.flags=0x00000004
# "Link on any PHYs" | "Static link speed"
hint.floatphy.1.speed=1000
#------------------------------------------------

Cavium Octeon CN5010 + BCM53115

Cavium Octeon CN5010, one NIC with three paths + BCM53115 switch + some Broadcom PHY. Since here is required a lot of magic to attach anything that Cavium was not expect as "can be attached" (i.e. Cavium SDK limitation), I made patch which allow to attach one PHY driver per NIC path (per octe0 iface).

VLAN features: it seems have most clear VLAN implementation, except some things like remapped some regs which have port bit maps. (seems forget to think about bigger port count when design small switches)

How to enable: Config:

#------------------------------------------------
device  brgphy
device  switch
device  switch_bcm5325
#------------------------------------------------

Hints:

#------------------------------------------------
hint.miibus.0.phymask="0x00000000"
hint.miibus.1.phymask="0x00000000"
hint.miibus.3.phymask="0x00000100"
# brgphy will attach here

hint.floatphy.0.at="miibus0"
hint.floatphy.0.phyno=0
hint.floatphy.0.master="switch"
hint.floatphy.0.master_unit=0
# Check link on any ports
hint.floatphy.0.master_phys=0x0000001f # Sense PHY0
hint.floatphy.0.flags=0x00000000
hint.floatphy.0.speed=1000

hint.switch.0.at="miibus1"
hint.switch.0.phyno=30
#------------------------------------------------

Links

1. Pics 2. patch

AleksandrRybalko/Switch Framework (last edited 2012-01-21 21:29:03 by AleksandrRybalko)