Intel Core(TM) PMCs
The following PMCs are present on Intel Core cpus:
- The TSC.
- 3 fixed function PMCs. As the name indicates, these counters handle a fixed kind of event each.
- 2 programmable PMCs. These are similar to the P6 PMCs, but not identical:
- While the PMCs reside at the same MSR addresses as the P6 PMCs, more bits in their registers have been specified.
- The semantics of Core PMC events have changed from the P6 ones. For example: event 0xC2, unit-mask 0 counts "uops-retired" on the P6. However, with Core PMCs, event 0xC2 requires one of six non-zero unit-mask values to be programmed; zero is not specified as a value for the unit-mask for this event.
The Core PMCs support more events than the P6. Some (but not all) of these events are core specific and need to be handled appropriately on multi-core CPUs.
- Event names used in Intel's manuals also differ from the P6 names; userland (and our documentation) thus needs to cope.
The good news is that starting with their Core architecture, Intel(R) has designated certain PMC events as 'architectural', meaning that they will henceforth be present in future revisions of their processors.