This page documents AMD/SVM support for bhyve. The work is being done in the projects/bhyve_svm branch. The intent is that the vmm.ko kernel module will support both Intel and AMD processors.
Page was last edited in 2013.
The code may make the 10.0 release - if not, it will be in 10.1.
- There are a number of MSRs that are unique to AMD and Intel - accessing these on the opposite architecture will result in a #GP fault. The MSR emulation code needs a way to allow the AMD/Intel modules to supply a list of MSRs that they will emulate, in addition to MSRs that are common.
- In a similar fashion, the CPUID emulation should have a way for AMD/Intel-specific code to override the common CPUID emulation.
SVM doesn't have a way to track NMI status of a guest in a similar way to Intel's NMI-shadow exit. In order to prevent NMIs from being injected into a guest that is already in NMI context, the shadow has to be tracked in s/w, perhaps by forcing an exit on the next iret.
The recent memory overcommit work integrated into CURRENT from the bhyve_npt branch needs to be implemented in SVM. This involves modifying the amd64 pmap.c code and implementing the SVM stubs that currently panic. In addition to this, a strategy for dealing with guest TLB entries using SVM ASIDs needs to be determined. There are enough differences between Intel guest TLB tagging with VPIDs and AMD ASIDs to make this a non-trivial problem.
bhyvectl needs to distinguish between Intel and AMD-specific guest state.
- To enable PCI pass-through, the AMD IOMMU needs to be implemented.
There appears to be a race in interrupt injection. This can be reproduced by generating large amounts of console traffic e.g. a number of find / commands in parallel. Eventually console output will halt since a uart fifo-empty interrupt will be lost. The VM will still be alive and can be ssh'd into etc. However, the console is effectively gone.