Clock and Power Management
Clock Mode |
Description |
Idle Low-Power (ILP) |
No register access is required, or long request latency is acceptable |
Active Low-Power (ALP) |
Low-latency register access and low-rate DMA. |
High Throughput (HT) |
High bus throughput and lowest-latency register access |
Hardware Revisions
There have been four major revisions to the PMU/clock management interface used in chipsets:
PWR_NONE
Clock management unsupported.
Applies to:
ChipCommon (revision <= 5)
PWR_CTL
Clocking is controlled device-wide via ChipCommon slow_clk_ctl register.
The XTAL and PLL must be enabled manually via GPIO registers; these are exposed via PCI config space registers.
Applies to:
ChipCommon (revision 6-9)
Capability Flag: CHIPC_CAP_PWR_CTL
PWR_CTL_INSTACLK
Clocking is controlled device-wide via ChipCommon system_clk_ctl register.
Applies to:
ChipCommon (revision 10-19)
Capability Flag: CHIPC_CAP_PWR_CTL
PMU
Clocking is managed automatically via per-device clock requests, exposed via a per-core clk_ctl_st register block.
Applies to:
PMU core or ChipCommon (revision >= 20)
Capability Flag: CHIPC_CAP_PMU
.----------. .----------. .-------------.
| RAM Core | | CPU Core | | PCI(e) Core |---------.
'-----.----' '-----.----' '------.------' |
| \ \ |
| \ clkreq \ clkreq v
v v v .......
.--------------------------------------------. . PCI .
| SoC Interconnect | .......
'--------------------------------------------'
^ clkreq | ^
.-----'----. v clkreq | clk(s)
| D11 Core | .--------------.-----------------.
'----------' | Clock Select | Clock Generator |
'--------------'-----------------'
^
|
.------.
| XTAL |
'------'