Attachment 'bhyve_hda.patch'
Download 1 Index: pci_hda.c
2 ===================================================================
3 --- pci_hda.c (revision 0)
4 +++ pci_hda.c (revision 307412)
5 @@ -0,0 +1,1337 @@
6 +
7 +#include <time.h>
8 +
9 +#include "pci_hda.h"
10 +#include "bhyverun.h"
11 +#include "pci_emul.h"
12 +#include "hdac_reg.h"
13 +
14 +/*
15 + * HDA defines
16 + */
17 +#define PCIR_HDCTL 0x40
18 +#define INTEL_VENDORID 0x8086
19 +#define HDA_INTEL_82801G 0x27d8
20 +
21 +#define HDA_IOSS_NO 0x08
22 +#define HDA_OSS_NO 0x04
23 +#define HDA_ISS_NO 0x04
24 +#define HDA_CODEC_MAX 0x0f
25 +#define HDA_LAST_OFFSET (0x2084 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
26 +#define HDA_SET_REG_TABLE_SZ (0x80 + ((HDA_ISS_NO) * 0x20) + ((HDA_OSS_NO) * 0x20))
27 +#define HDA_CORB_ENTRY_LEN 0x04
28 +#define HDA_RIRB_ENTRY_LEN 0x08
29 +#define HDA_BDL_ENTRY_LEN 0x10
30 +#define HDA_DMA_PIB_ENTRY_LEN 0x08
31 +#define HDA_STREAM_TAGS_CNT 0x10
32 +#define HDA_STREAM_REGS_BASE 0x80
33 +#define HDA_STREAM_REGS_LEN 0x20
34 +
35 +#define HDA_DMA_ACCESS_LEN (sizeof(uint32_t))
36 +#define HDA_BDL_MAX_LEN 0x0100
37 +
38 +#define HDAC_SDSTS_FIFORDY (1 << 5)
39 +
40 +#define HDA_RIRBSTS_IRQ_MASK (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS)
41 +#define HDA_STATESTS_IRQ_MASK ((1 << HDA_CODEC_MAX) - 1)
42 +#define HDA_SDSTS_IRQ_MASK (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS)
43 +
44 +/*
45 + * HDA data structures
46 + */
47 +
48 +struct hda_softc;
49 +
50 +typedef void (*hda_set_reg_handler)(struct hda_softc *sc, uint32_t offset, uint32_t old);
51 +
52 +struct hda_bdle {
53 + uint32_t addrl;
54 + uint32_t addrh;
55 + uint32_t len;
56 + uint32_t ioc;
57 +} __packed;
58 +
59 +struct hda_bdle_desc {
60 + void *addr;
61 + uint32_t len;
62 + uint8_t ioc;
63 +};
64 +
65 +struct hda_codec_cmd_ctl {
66 + char *name;
67 + void *dma_vaddr;
68 + uint16_t size;
69 + uint16_t wp;
70 + uint16_t rp;
71 + uint8_t run;
72 +};
73 +
74 +struct hda_stream_desc {
75 + uint8_t stream;
76 + uint8_t run;
77 + uint8_t dir;
78 +
79 + /* bp is the no. of bytes transferred in the current bdle */
80 + uint32_t bp;
81 + /* be is the no. of bdles transferred in the bdl */
82 + uint32_t be;
83 +
84 + struct hda_bdle_desc bdl[HDA_BDL_MAX_LEN];
85 + uint32_t bdl_cnt;
86 +};
87 +
88 +struct hda_softc {
89 + struct pci_devinst *pci_dev;
90 + uint32_t regs[HDA_LAST_OFFSET];
91 +
92 + uint8_t lintr;
93 + uint8_t rirb_cnt;
94 + uint64_t wall_clock_start;
95 +
96 + struct hda_codec_cmd_ctl corb;
97 + struct hda_codec_cmd_ctl rirb;
98 +
99 + struct hda_codec_inst *codecs[HDA_CODEC_MAX];
100 + uint8_t codecs_no;
101 +
102 + /* Base Address of the DMA Position Buffer */
103 + void *dma_pib_vaddr;
104 +
105 + struct hda_stream_desc streams[HDA_IOSS_NO];
106 + /* 2 tables for output and input */
107 + uint8_t stream_map[2][HDA_STREAM_TAGS_CNT];
108 +};
109 +
110 +/*
111 + * HDA module function declarations
112 + */
113 +static inline void
114 +hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t value);
115 +static inline uint32_t
116 +hda_get_reg_by_offset(struct hda_softc *sc, uint32_t offset);
117 +static inline void
118 +hda_set_field_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t mask, uint32_t value);
119 +
120 +static uint8_t
121 +hda_parse_config(const char *opts, const char *key, char *val);
122 +static struct hda_softc *hda_init(const char *opts);
123 +static void
124 +hda_update_intr(struct hda_softc *sc);
125 +static void
126 +hda_response_interrupt(struct hda_softc *sc);
127 +static int
128 +hda_codec_constructor(struct hda_softc *sc, struct hda_codec_class *codec,
129 + const char *play, const char *rec, const char *opts);
130 +static struct hda_codec_class *
131 +hda_find_codec_class(const char *name);
132 +
133 +static int
134 +hda_send_command(struct hda_softc *sc, uint32_t verb);
135 +static int
136 +hda_notify_codecs(struct hda_softc *sc, uint8_t run, uint8_t stream, uint8_t dir);
137 +static void
138 +hda_reset(struct hda_softc *sc);
139 +static void
140 +hda_reset_regs(struct hda_softc *sc);
141 +static void
142 +hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind);
143 +static int
144 +hda_stream_start(struct hda_softc *sc, uint8_t stream_ind);
145 +static int
146 +hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind);
147 +static uint32_t
148 +hda_read(struct hda_softc *sc, uint32_t offset);
149 +static int
150 +hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size, uint32_t value);
151 +
152 +static inline void
153 +hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p);
154 +static int
155 +hda_corb_start(struct hda_softc *sc);
156 +static int
157 +hda_corb_run(struct hda_softc *sc);
158 +static int
159 +hda_rirb_start(struct hda_softc *sc);
160 +
161 +static void *
162 +hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr, size_t len);
163 +static void
164 +hda_dma_st_dword(void *dma_vaddr, uint32_t data);
165 +static uint32_t
166 +hda_dma_ld_dword(void *dma_vaddr);
167 +
168 +static inline uint8_t
169 +hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset);
170 +static inline uint32_t
171 +hda_get_offset_stream(uint8_t stream_ind);
172 +
173 +static void
174 +hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
175 +static void
176 +hda_set_statests(struct hda_softc *sc, uint32_t offset, uint32_t old);
177 +static void
178 +hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old);
179 +static void
180 +hda_set_corbctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
181 +static void
182 +hda_set_rirbctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
183 +static void
184 +hda_set_rirbsts(struct hda_softc *sc, uint32_t offset, uint32_t old);
185 +static void
186 +hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset, uint32_t old);
187 +static void
188 +hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old);
189 +static void
190 +hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old);
191 +static void
192 +hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old);
193 +
194 +static int
195 +hda_signal_state_change(struct hda_codec_inst *hci);
196 +static int
197 +hda_response(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol);
198 +static int
199 +hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir, void *buf, size_t count);
200 +
201 +static void
202 +hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib);
203 +static uint64_t hda_get_clock_ns(void);
204 +
205 +/*
206 + * PCI HDA function declarations
207 + */
208 +static int
209 +pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts);
210 +static void
211 +pci_hda_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
212 + int baridx, uint64_t offset, int size, uint64_t value);
213 +static uint64_t
214 +pci_hda_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
215 + int baridx, uint64_t offset, int size);
216 +/*
217 + * HDA global data
218 + */
219 +
220 +static const hda_set_reg_handler hda_set_reg_table[] = {
221 + [HDAC_GCTL] = hda_set_gctl,
222 + [HDAC_STATESTS] = hda_set_statests,
223 + [HDAC_CORBWP] = hda_set_corbwp,
224 + [HDAC_CORBCTL] = hda_set_corbctl,
225 + [HDAC_RIRBCTL] = hda_set_rirbctl,
226 + [HDAC_RIRBSTS] = hda_set_rirbsts,
227 + [HDAC_DPIBLBASE] = hda_set_dpiblbase,
228 +
229 +#define HDAC_ISTREAM(n, iss, oss) \
230 + [_HDAC_ISDCTL(n, iss, oss)] = hda_set_sdctl, \
231 + [_HDAC_ISDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
232 + [_HDAC_ISDSTS(n, iss, oss)] = hda_set_sdsts, \
233 +
234 +#define HDAC_OSTREAM(n, iss, oss) \
235 + [_HDAC_OSDCTL(n, iss, oss)] = hda_set_sdctl, \
236 + [_HDAC_OSDCTL(n, iss, oss) + 2] = hda_set_sdctl2, \
237 + [_HDAC_OSDSTS(n, iss, oss)] = hda_set_sdsts, \
238 +
239 + HDAC_ISTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
240 + HDAC_ISTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
241 + HDAC_ISTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
242 + HDAC_ISTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
243 +
244 + HDAC_OSTREAM(0, HDA_ISS_NO, HDA_OSS_NO)
245 + HDAC_OSTREAM(1, HDA_ISS_NO, HDA_OSS_NO)
246 + HDAC_OSTREAM(2, HDA_ISS_NO, HDA_OSS_NO)
247 + HDAC_OSTREAM(3, HDA_ISS_NO, HDA_OSS_NO)
248 +
249 + [HDA_SET_REG_TABLE_SZ] = NULL,
250 +};
251 +
252 +static const uint16_t hda_corb_sizes[] = {
253 + [HDAC_CORBSIZE_CORBSIZE_2] = 2,
254 + [HDAC_CORBSIZE_CORBSIZE_16] = 16,
255 + [HDAC_CORBSIZE_CORBSIZE_256] = 256,
256 + [HDAC_CORBSIZE_CORBSIZE_MASK] = 0,
257 +};
258 +
259 +static const uint16_t hda_rirb_sizes[] = {
260 + [HDAC_RIRBSIZE_RIRBSIZE_2] = 2,
261 + [HDAC_RIRBSIZE_RIRBSIZE_16] = 16,
262 + [HDAC_RIRBSIZE_RIRBSIZE_256] = 256,
263 + [HDAC_RIRBSIZE_RIRBSIZE_MASK] = 0,
264 +};
265 +
266 +static struct hda_ops hops = {
267 + .signal = hda_signal_state_change,
268 + .response = hda_response,
269 + .transfer = hda_transfer,
270 +};
271 +
272 +struct pci_devemu pci_de_hda = {
273 + .pe_emu = "hda",
274 + .pe_init = pci_hda_init,
275 + .pe_barwrite = pci_hda_write,
276 + .pe_barread = pci_hda_read
277 +};
278 +
279 +PCI_EMUL_SET(pci_de_hda);
280 +
281 +SET_DECLARE(hda_codec_class_set, struct hda_codec_class);
282 +
283 +#if DEBUG_HDA == 1
284 +FILE *dbg;
285 +#endif
286 +
287 +/*
288 + * HDA module function definitions
289 + */
290 +
291 +static inline void
292 +hda_set_reg_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t value)
293 +{
294 + assert(offset < HDA_LAST_OFFSET);
295 + sc->regs[offset] = value;
296 +
297 + return;
298 +}
299 +
300 +static inline uint32_t
301 +hda_get_reg_by_offset(struct hda_softc *sc, uint32_t offset)
302 +{
303 + assert(offset < HDA_LAST_OFFSET);
304 + return sc->regs[offset];
305 +}
306 +
307 +static inline void
308 +hda_set_field_by_offset(struct hda_softc *sc, uint32_t offset, uint32_t mask, uint32_t value)
309 +{
310 + uint32_t reg_value = 0;
311 +
312 + reg_value = hda_get_reg_by_offset(sc, offset);
313 +
314 + reg_value &= ~mask;
315 + reg_value |= (value & mask);
316 +
317 + hda_set_reg_by_offset(sc, offset, reg_value);
318 +
319 + return;
320 +}
321 +
322 +static uint8_t
323 +hda_parse_config(const char *opts, const char *key, char *val)
324 +{
325 + char buf[64];
326 + char *s = buf;
327 + char *tmp = NULL;
328 + int len;
329 + int i;
330 +
331 + if (!opts)
332 + return 0;
333 +
334 + len = strlen(opts);
335 +
336 + if (len >= 64) {
337 + DPRINTF("Opts too big\n");
338 + return 0;
339 + }
340 +
341 + DPRINTF("opts: %s\n", opts);
342 +
343 + strcpy(buf, opts);
344 +
345 + for (i = 0; i < len; i++)
346 + if (buf[i] == ',') {
347 + buf[i] = 0;
348 + tmp = buf + i + 1;
349 + break;
350 + }
351 +
352 + if (!memcmp(s, key, strlen(key))) {
353 + strncpy(val, s + strlen(key), 64);
354 + return 1;
355 + }
356 +
357 + if (!tmp)
358 + return 0;
359 +
360 + s = tmp;
361 + if (!memcmp(s, key, strlen(key))) {
362 + strncpy(val, s + strlen(key), 64);
363 + return 1;
364 + }
365 +
366 + return 0;
367 +}
368 +
369 +static struct hda_softc *hda_init(const char *opts)
370 +{
371 + struct hda_softc *sc = NULL;
372 + struct hda_codec_class *codec = NULL;
373 + char play[64];
374 + char rec[64];
375 + int err, p, r;
376 +
377 +#if DEBUG_HDA == 1
378 + dbg = fopen("/tmp/bhyve_hda.log", "w+");
379 +#endif
380 +
381 + DPRINTF("opts: %s\n", opts);
382 +
383 + sc = calloc(1, sizeof(*sc));
384 + if (!sc)
385 + return NULL;
386 +
387 + hda_reset_regs(sc);
388 +
389 + /*
390 + * TODO search all the codecs declared in opts
391 + * For now we play with one single codec
392 + */
393 + codec = hda_find_codec_class("hda_codec");
394 + if (codec) {
395 + p = hda_parse_config(opts, "play=", play);
396 + r = hda_parse_config(opts, "rec=", rec);
397 + DPRINTF("play: %s rec: %s\n", play, rec);
398 + if (p | r) {
399 + err = hda_codec_constructor(sc, codec, p ? play : NULL, r ? rec : NULL, NULL);
400 + assert(!err);
401 + }
402 + }
403 +
404 + return sc;
405 +}
406 +
407 +static void
408 +hda_update_intr(struct hda_softc *sc)
409 +{
410 + struct pci_devinst *pi = sc->pci_dev;
411 + uint32_t intctl = hda_get_reg_by_offset(sc, HDAC_INTCTL);
412 + uint32_t intsts = 0;
413 + uint32_t sdsts = 0;
414 + uint32_t rirbsts = 0;
415 + uint32_t wakeen = 0;
416 + uint32_t statests = 0;
417 + uint32_t off = 0;
418 + int i;
419 +
420 + /* update the CIS bits */
421 + rirbsts = hda_get_reg_by_offset(sc, HDAC_RIRBSTS);
422 + if (rirbsts & (HDAC_RIRBSTS_RINTFL | HDAC_RIRBSTS_RIRBOIS))
423 + intsts |= HDAC_INTSTS_CIS;
424 +
425 + wakeen = hda_get_reg_by_offset(sc, HDAC_WAKEEN);
426 + statests = hda_get_reg_by_offset(sc, HDAC_STATESTS);
427 + if (statests & wakeen)
428 + intsts |= HDAC_INTSTS_CIS;
429 +
430 + /* update the SIS bits */
431 + for (i = 0; i < HDA_IOSS_NO; i++) {
432 + off = hda_get_offset_stream(i);
433 + sdsts = hda_get_reg_by_offset(sc, off + HDAC_SDSTS);
434 + if (sdsts & HDAC_SDSTS_BCIS)
435 + intsts |= (1 << i);
436 + }
437 +
438 + /* update the GIS bit */
439 + if (intsts)
440 + intsts |= HDAC_INTSTS_GIS;
441 +
442 + hda_set_reg_by_offset(sc, HDAC_INTSTS, intsts);
443 +
444 + if ((intctl & HDAC_INTCTL_GIE) && ((intsts & ~HDAC_INTSTS_GIS) & intctl)) {
445 + if (!sc->lintr) {
446 + pci_lintr_assert(pi);
447 + sc->lintr = 1;
448 + }
449 + } else {
450 + if (sc->lintr) {
451 + pci_lintr_deassert(pi);
452 + sc->lintr = 0;
453 + }
454 + }
455 +
456 + return;
457 +}
458 +
459 +static void
460 +hda_response_interrupt(struct hda_softc *sc)
461 +{
462 + uint8_t rirbctl = hda_get_reg_by_offset(sc, HDAC_RIRBCTL);
463 +
464 + if ((rirbctl & HDAC_RIRBCTL_RINTCTL) && sc->rirb_cnt) {
465 + sc->rirb_cnt = 0;
466 + hda_set_field_by_offset(sc, HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL, HDAC_RIRBSTS_RINTFL);
467 + hda_update_intr(sc);
468 + }
469 +
470 + return;
471 +}
472 +
473 +static int
474 +hda_codec_constructor(struct hda_softc *sc, struct hda_codec_class *codec,
475 + const char *play, const char *rec, const char *opts)
476 +{
477 + struct hda_codec_inst *hci = NULL;
478 +
479 + if (sc->codecs_no >= HDA_CODEC_MAX)
480 + return -1;
481 +
482 + hci = calloc(1, sizeof(struct hda_codec_inst));
483 + if (!hci)
484 + return -1;
485 +
486 + hci->hda = sc;
487 + hci->hops = &hops;
488 + hci->cad = sc->codecs_no;
489 + hci->codec = codec;
490 +
491 + sc->codecs[sc->codecs_no++] = hci;
492 +
493 + if (!codec->init) {
494 + DPRINTF("This codec does not implement the init function\n");
495 + return -1;
496 + }
497 +
498 + return codec->init(hci, play, rec, opts);
499 +}
500 +
501 +static struct hda_codec_class *
502 +hda_find_codec_class(const char *name)
503 +{
504 + struct hda_codec_class **pdpp = NULL, *pdp = NULL;
505 +
506 + SET_FOREACH(pdpp, hda_codec_class_set) {
507 + pdp = *pdpp;
508 + if (!strcmp(pdp->name, name)) {
509 + return (pdp);
510 + }
511 + }
512 +
513 + return NULL;
514 +}
515 +
516 +static int
517 +hda_send_command(struct hda_softc *sc, uint32_t verb)
518 +{
519 + struct hda_codec_inst *hci = NULL;
520 + struct hda_codec_class *codec = NULL;
521 + uint8_t cad = (verb >> HDA_CMD_CAD_SHIFT) & 0x0f;
522 +
523 + hci = sc->codecs[cad];
524 + if (!hci)
525 + return -1;
526 +
527 + DPRINTF("cad: 0x%x verb: 0x%x\n", cad, verb);
528 +
529 + codec = hci->codec;
530 + assert(codec);
531 +
532 + if (!codec->command) {
533 + DPRINTF("This codec does not implement the command function\n");
534 + return -1;
535 + }
536 +
537 + return codec->command(hci, verb);
538 +}
539 +
540 +static int
541 +hda_notify_codecs(struct hda_softc *sc, uint8_t run, uint8_t stream, uint8_t dir)
542 +{
543 + struct hda_codec_inst *hci = NULL;
544 + struct hda_codec_class *codec = NULL;
545 + int err;
546 + int i;
547 +
548 + /* Notify each codec */
549 + for (i = 0; i < sc->codecs_no; i++) {
550 + hci = sc->codecs[i];
551 + assert(hci);
552 +
553 + codec = hci->codec;
554 + assert(codec);
555 +
556 + if (codec->notify) {
557 + err = codec->notify(hci, run, stream, dir);
558 + if (!err)
559 + break;
560 + }
561 + }
562 +
563 + return i == sc->codecs_no ? (-1) : 0;
564 +}
565 +
566 +static void
567 +hda_reset(struct hda_softc *sc)
568 +{
569 + int i;
570 + struct hda_codec_inst *hci = NULL;
571 + struct hda_codec_class *codec = NULL;
572 +
573 + hda_reset_regs(sc);
574 +
575 + /* Reset each codec */
576 + for (i = 0; i < sc->codecs_no; i++) {
577 + hci = sc->codecs[i];
578 + assert(hci);
579 +
580 + codec = hci->codec;
581 + assert(codec);
582 +
583 + if (codec->reset)
584 + codec->reset(hci);
585 + }
586 +
587 + sc->wall_clock_start = hda_get_clock_ns();
588 +
589 + return;
590 +}
591 +
592 +static void
593 +hda_reset_regs(struct hda_softc *sc)
594 +{
595 + uint32_t off = 0;
596 + uint8_t i;
597 +
598 + DPRINTF("Reset the HDA controller registers ...\n");
599 +
600 + memset(sc->regs, 0, sizeof(sc->regs));
601 +
602 + hda_set_reg_by_offset(sc, HDAC_GCAP,
603 + HDAC_GCAP_64OK |
604 + (HDA_ISS_NO << HDAC_GCAP_ISS_SHIFT) |
605 + (HDA_OSS_NO << HDAC_GCAP_OSS_SHIFT));
606 + hda_set_reg_by_offset(sc, HDAC_VMAJ, 0x01);
607 + hda_set_reg_by_offset(sc, HDAC_OUTPAY, 0x3c);
608 + hda_set_reg_by_offset(sc, HDAC_INPAY, 0x1d);
609 + hda_set_reg_by_offset(sc, HDAC_CORBSIZE, HDAC_CORBSIZE_CORBSZCAP_256 | HDAC_CORBSIZE_CORBSIZE_256);
610 + hda_set_reg_by_offset(sc, HDAC_RIRBSIZE, HDAC_RIRBSIZE_RIRBSZCAP_256 | HDAC_RIRBSIZE_RIRBSIZE_256);
611 +
612 + for (i = 0; i < HDA_IOSS_NO; i++) {
613 + off = hda_get_offset_stream(i);
614 + hda_set_reg_by_offset(sc, off + HDAC_SDFIFOS, HDA_FIFO_SIZE);
615 + }
616 +
617 + return;
618 +}
619 +
620 +static void
621 +hda_stream_reset(struct hda_softc *sc, uint8_t stream_ind)
622 +{
623 + struct hda_stream_desc *st = &sc->streams[stream_ind];
624 + uint32_t off = hda_get_offset_stream(stream_ind);
625 +
626 + DPRINTF("Reset the HDA stream: 0x%x\n", stream_ind);
627 +
628 + /* Reset the Stream Descriptor registers */
629 + memset(sc->regs + HDA_STREAM_REGS_BASE + off, 0, HDA_STREAM_REGS_LEN);
630 +
631 + /* Reset the Stream Descriptor */
632 + memset(st, 0, sizeof(*st));
633 +
634 + hda_set_field_by_offset(sc, off + HDAC_SDSTS, HDAC_SDSTS_FIFORDY, HDAC_SDSTS_FIFORDY);
635 + hda_set_field_by_offset(sc, off + HDAC_SDCTL0, HDAC_SDCTL_SRST, HDAC_SDCTL_SRST);
636 +
637 + return;
638 +}
639 +
640 +static int
641 +hda_stream_start(struct hda_softc *sc, uint8_t stream_ind)
642 +{
643 + struct hda_stream_desc *st = &sc->streams[stream_ind];
644 + struct hda_bdle_desc *bdle_desc = NULL;
645 + struct hda_bdle *bdle = NULL;
646 + uint32_t lvi = 0;
647 + uint32_t bdl_cnt = 0;
648 + uint64_t bdpl = 0;
649 + uint64_t bdpu = 0;
650 + uint64_t bdl_paddr = 0;
651 + void *bdl_vaddr = NULL;
652 + uint32_t bdle_sz = 0;
653 + uint64_t bdle_addrl = 0;
654 + uint64_t bdle_addrh = 0;
655 + uint64_t bdle_paddr = 0;
656 + void *bdle_vaddr = NULL;
657 + uint32_t off = hda_get_offset_stream(stream_ind);
658 + uint32_t sdctl = 0;
659 + uint8_t strm = 0;
660 + uint8_t dir = 0;
661 + int i;
662 +
663 + assert(!st->run);
664 +
665 + lvi = hda_get_reg_by_offset(sc, off + HDAC_SDLVI);
666 + bdpl = hda_get_reg_by_offset(sc, off + HDAC_SDBDPL);
667 + bdpu = hda_get_reg_by_offset(sc, off + HDAC_SDBDPU);
668 +
669 + bdl_cnt = lvi + 1;
670 + assert(bdl_cnt <= HDA_BDL_MAX_LEN);
671 +
672 + bdl_paddr = bdpl | (bdpu << 32);
673 + bdl_vaddr = hda_dma_get_vaddr(sc, bdl_paddr, HDA_BDL_ENTRY_LEN * bdl_cnt);
674 + if (!bdl_vaddr) {
675 + DPRINTF("Fail to get the guest virtual address\n");
676 + return -1;
677 + }
678 +
679 + DPRINTF("stream: 0x%x bdl_cnt: 0x%x bdl_paddr: 0x%lx\n", stream_ind, bdl_cnt, bdl_paddr);
680 +
681 + st->bdl_cnt = bdl_cnt;
682 +
683 + bdle = (struct hda_bdle *)bdl_vaddr;
684 + for (i = 0; i < bdl_cnt; i++, bdle++) {
685 + bdle_sz = bdle->len;
686 + assert(!(bdle_sz % HDA_DMA_ACCESS_LEN));
687 +
688 + bdle_addrl = bdle->addrl;
689 + bdle_addrh = bdle->addrh;
690 +
691 + bdle_paddr = bdle_addrl | (bdle_addrh << 32);
692 + bdle_vaddr = hda_dma_get_vaddr(sc, bdle_paddr, bdle_sz);
693 + if (!bdle_vaddr) {
694 + DPRINTF("Fail to get the guest virtual address\n");
695 + return -1;
696 + }
697 +
698 + bdle_desc = &st->bdl[i];
699 + bdle_desc->addr = bdle_vaddr;
700 + bdle_desc->len = bdle_sz;
701 + bdle_desc->ioc = bdle->ioc;
702 +
703 + DPRINTF("bdle: 0x%x bdle_sz: 0x%x\n", i, bdle_sz);
704 + }
705 +
706 + sdctl = hda_get_reg_by_offset(sc, off + HDAC_SDCTL0);
707 + strm = (sdctl >> 20) & 0x0f;
708 + dir = stream_ind >= HDA_ISS_NO;
709 +
710 + DPRINTF("strm: 0x%x, dir: 0x%x\n", strm, dir);
711 +
712 + sc->stream_map[dir][strm] = stream_ind;
713 + st->stream = strm;
714 + st->dir = dir;
715 + st->bp = 0;
716 + st->be = 0;
717 +
718 + hda_set_pib(sc, stream_ind, 0);
719 +
720 + st->run = 1;
721 +
722 + hda_notify_codecs(sc, 1, strm, dir);
723 +
724 + return 0;
725 +}
726 +
727 +static int
728 +hda_stream_stop(struct hda_softc *sc, uint8_t stream_ind)
729 +{
730 + struct hda_stream_desc *st = &sc->streams[stream_ind];
731 + uint8_t strm = st->stream;
732 + uint8_t dir = st->dir;
733 +
734 + DPRINTF("stream: 0x%x, strm: 0x%x, dir: 0x%x\n", stream_ind, strm, dir);
735 +
736 + st->run = 0;
737 +
738 + hda_notify_codecs(sc, 0, strm, dir);
739 +
740 + return 0;
741 +}
742 +
743 +static uint32_t
744 +hda_read(struct hda_softc *sc, uint32_t offset)
745 +{
746 + if (offset == HDAC_WALCLK)
747 + return (24 * (hda_get_clock_ns() - sc->wall_clock_start) / 1000);
748 +
749 + return hda_get_reg_by_offset(sc, offset);
750 +}
751 +
752 +static int
753 +hda_write(struct hda_softc *sc, uint32_t offset, uint8_t size, uint32_t value)
754 +{
755 + uint32_t old = hda_get_reg_by_offset(sc, offset);
756 + uint32_t masks[] = {0x00000000, 0x000000ff, 0x0000ffff, 0x00ffffff, 0xffffffff};
757 + hda_set_reg_handler set_reg_handler = hda_set_reg_table[offset];
758 +
759 + hda_set_field_by_offset(sc, offset, masks[size], value);
760 +
761 + if (set_reg_handler)
762 + set_reg_handler(sc, offset, old);
763 +
764 + return 0;
765 +}
766 +
767 +static inline void
768 +hda_print_cmd_ctl_data(struct hda_codec_cmd_ctl *p)
769 +{
770 +#if DEBUG_HDA == 1
771 + char *name = p->name;
772 +#endif
773 + DPRINTF("%s size: %d\n", name, p->size);
774 + DPRINTF("%s dma_vaddr: %p\n", name, p->dma_vaddr);
775 + DPRINTF("%s wp: 0x%x\n", name, p->wp);
776 + DPRINTF("%s rp: 0x%x\n", name, p->rp);
777 +
778 + return;
779 +}
780 +
781 +static int
782 +hda_corb_start(struct hda_softc *sc)
783 +{
784 + struct hda_codec_cmd_ctl *corb = &sc->corb;
785 + uint8_t corbsize = 0;
786 + uint64_t corblbase = 0;
787 + uint64_t corbubase = 0;
788 + uint64_t corbpaddr = 0;
789 +
790 + corb->name = "CORB";
791 +
792 + corbsize = hda_get_reg_by_offset(sc, HDAC_CORBSIZE) & HDAC_CORBSIZE_CORBSIZE_MASK;
793 + corb->size = hda_corb_sizes[corbsize];
794 +
795 + if (!corb->size) {
796 + DPRINTF("Invalid corb size\n");
797 + return -1;
798 + }
799 +
800 + corblbase = hda_get_reg_by_offset(sc, HDAC_CORBLBASE);
801 + corbubase = hda_get_reg_by_offset(sc, HDAC_CORBUBASE);
802 +
803 + corbpaddr = corblbase | (corbubase << 32);
804 + DPRINTF("CORB dma_paddr: %p\n", (void *)corbpaddr);
805 +
806 + corb->dma_vaddr = hda_dma_get_vaddr(sc, corbpaddr, HDA_CORB_ENTRY_LEN * corb->size);
807 + if (!corb->dma_vaddr) {
808 + DPRINTF("Fail to get the guest virtual address\n");
809 + return -1;
810 + }
811 +
812 + corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
813 + corb->rp = hda_get_reg_by_offset(sc, HDAC_CORBRP);
814 +
815 + corb->run = 1;
816 +
817 + hda_print_cmd_ctl_data(corb);
818 +
819 + return 0;
820 +}
821 +
822 +static int
823 +hda_corb_run(struct hda_softc *sc)
824 +{
825 + struct hda_codec_cmd_ctl *corb = &sc->corb;
826 + uint32_t verb = 0;
827 + int err;
828 +
829 + corb->wp = hda_get_reg_by_offset(sc, HDAC_CORBWP);
830 +
831 + while (corb->rp != corb->wp && corb->run) {
832 + corb->rp++;
833 + corb->rp %= corb->size;
834 +
835 + verb = hda_dma_ld_dword(corb->dma_vaddr + HDA_CORB_ENTRY_LEN * corb->rp);
836 +
837 + err = hda_send_command(sc, verb);
838 + assert(!err);
839 + }
840 +
841 + hda_set_reg_by_offset(sc, HDAC_CORBRP, corb->rp);
842 +
843 + if (corb->run)
844 + hda_response_interrupt(sc);
845 +
846 + return 0;
847 +}
848 +
849 +static int
850 +hda_rirb_start(struct hda_softc *sc)
851 +{
852 + struct hda_codec_cmd_ctl *rirb = &sc->rirb;
853 + uint8_t rirbsize = 0;
854 + uint64_t rirblbase = 0;
855 + uint64_t rirbubase = 0;
856 + uint64_t rirbpaddr = 0;
857 +
858 + rirb->name = "RIRB";
859 +
860 + rirbsize = hda_get_reg_by_offset(sc, HDAC_RIRBSIZE) & HDAC_RIRBSIZE_RIRBSIZE_MASK;
861 + rirb->size = hda_rirb_sizes[rirbsize];
862 +
863 + if (!rirb->size) {
864 + DPRINTF("Invalid rirb size\n");
865 + return -1;
866 + }
867 +
868 + rirblbase = hda_get_reg_by_offset(sc, HDAC_RIRBLBASE);
869 + rirbubase = hda_get_reg_by_offset(sc, HDAC_RIRBUBASE);
870 +
871 + rirbpaddr = rirblbase | (rirbubase << 32);
872 + DPRINTF("RIRB dma_paddr: %p\n", (void *)rirbpaddr);
873 +
874 + rirb->dma_vaddr = hda_dma_get_vaddr(sc, rirbpaddr, HDA_RIRB_ENTRY_LEN * rirb->size);
875 + if (!rirb->dma_vaddr) {
876 + DPRINTF("Fail to get the guest virtual address\n");
877 + return -1;
878 + }
879 +
880 + rirb->wp = hda_get_reg_by_offset(sc, HDAC_RIRBWP);
881 + rirb->rp = 0x0000;
882 +
883 + rirb->run = 1;
884 +
885 + hda_print_cmd_ctl_data(rirb);
886 +
887 + return 0;
888 +}
889 +
890 +static void *
891 +hda_dma_get_vaddr(struct hda_softc *sc, uint64_t dma_paddr, size_t len)
892 +{
893 + struct pci_devinst *pi = sc->pci_dev;
894 +
895 + assert(pi);
896 +
897 + return paddr_guest2host(pi->pi_vmctx, (uintptr_t)dma_paddr, len);
898 +}
899 +
900 +static void
901 +hda_dma_st_dword(void *dma_vaddr, uint32_t data)
902 +{
903 + *(uint32_t*)dma_vaddr = data;
904 +
905 + return;
906 +}
907 +
908 +static uint32_t
909 +hda_dma_ld_dword(void *dma_vaddr)
910 +{
911 + return *(uint32_t*)dma_vaddr;
912 +}
913 +
914 +static inline uint8_t
915 +hda_get_stream_by_offsets(uint32_t offset, uint8_t reg_offset)
916 +{
917 + uint8_t stream_ind = (offset - reg_offset) >> 5;
918 +
919 + assert(stream_ind < HDA_IOSS_NO);
920 +
921 + return stream_ind;
922 +}
923 +
924 +static inline uint32_t
925 +hda_get_offset_stream(uint8_t stream_ind)
926 +{
927 + return stream_ind << 5;
928 +}
929 +
930 +static void
931 +hda_set_gctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
932 +{
933 + uint32_t value = hda_get_reg_by_offset(sc, offset);
934 +
935 + if (!(value & HDAC_GCTL_CRST)) {
936 + hda_reset(sc);
937 + }
938 +
939 + return;
940 +}
941 +
942 +static void
943 +hda_set_statests(struct hda_softc *sc, uint32_t offset, uint32_t old)
944 +{
945 + uint32_t value = hda_get_reg_by_offset(sc, offset);
946 +
947 + hda_set_reg_by_offset(sc, offset, old);
948 +
949 + /* clear the corresponding bits written by the software (guest) */
950 + hda_set_field_by_offset(sc, offset, value & HDA_STATESTS_IRQ_MASK, 0);
951 +
952 + hda_update_intr(sc);
953 +
954 + return;
955 +}
956 +
957 +static void
958 +hda_set_corbwp(struct hda_softc *sc, uint32_t offset, uint32_t old)
959 +{
960 + hda_corb_run(sc);
961 +
962 + return;
963 +}
964 +
965 +static void
966 +hda_set_corbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
967 +{
968 + uint32_t value = hda_get_reg_by_offset(sc, offset);
969 + int err;
970 + struct hda_codec_cmd_ctl *corb = NULL;
971 +
972 + if (value & HDAC_CORBCTL_CORBRUN) {
973 + if (!(old & HDAC_CORBCTL_CORBRUN)) {
974 + err = hda_corb_start(sc);
975 + assert(!err);
976 + }
977 + } else {
978 + corb = &sc->corb;
979 + memset(corb, 0, sizeof(*corb));
980 + }
981 +
982 + hda_corb_run(sc);
983 +
984 + return;
985 +}
986 +
987 +static void
988 +hda_set_rirbctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
989 +{
990 + uint32_t value = hda_get_reg_by_offset(sc, offset);
991 + int err;
992 + struct hda_codec_cmd_ctl *rirb = NULL;
993 +
994 + if (value & HDAC_RIRBCTL_RIRBDMAEN) {
995 + err = hda_rirb_start(sc);
996 + assert(!err);
997 + } else {
998 + rirb = &sc->rirb;
999 + memset(rirb, 0, sizeof(*rirb));
1000 + }
1001 +
1002 + return;
1003 +}
1004 +
1005 +static void
1006 +hda_set_rirbsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
1007 +{
1008 + uint32_t value = hda_get_reg_by_offset(sc, offset);
1009 +
1010 + hda_set_reg_by_offset(sc, offset, old);
1011 +
1012 + /* clear the corresponding bits written by the software (guest) */
1013 + hda_set_field_by_offset(sc, offset, value & HDA_RIRBSTS_IRQ_MASK, 0);
1014 +
1015 + hda_update_intr(sc);
1016 +
1017 + return;
1018 +}
1019 +
1020 +static void
1021 +hda_set_dpiblbase(struct hda_softc *sc, uint32_t offset, uint32_t old)
1022 +{
1023 + uint32_t value = hda_get_reg_by_offset(sc, offset);
1024 + uint64_t dpiblbase = 0;
1025 + uint64_t dpibubase = 0;
1026 + uint64_t dpibpaddr = 0;
1027 +
1028 + if ((value & HDAC_DPLBASE_DPLBASE_DMAPBE) != (old & HDAC_DPLBASE_DPLBASE_DMAPBE)) {
1029 + if (value & HDAC_DPLBASE_DPLBASE_DMAPBE) {
1030 + dpiblbase = value & HDAC_DPLBASE_DPLBASE_MASK;
1031 + dpibubase = hda_get_reg_by_offset(sc, HDAC_DPIBUBASE);
1032 +
1033 + dpibpaddr = dpiblbase | (dpibubase << 32);
1034 + DPRINTF("DMA Position In Buffer dma_paddr: %p\n", (void *)dpibpaddr);
1035 +
1036 + sc->dma_pib_vaddr = hda_dma_get_vaddr(sc, dpibpaddr, HDA_DMA_PIB_ENTRY_LEN * HDA_IOSS_NO);
1037 + if (!sc->dma_pib_vaddr) {
1038 + DPRINTF("Fail to get the guest virtual address\n");
1039 + assert(0);
1040 + }
1041 + } else {
1042 + DPRINTF("DMA Position In Buffer Reset\n");
1043 + sc->dma_pib_vaddr = NULL;
1044 + }
1045 + }
1046 +
1047 + return;
1048 +}
1049 +
1050 +static void
1051 +hda_set_sdctl(struct hda_softc *sc, uint32_t offset, uint32_t old)
1052 +{
1053 + uint8_t stream_ind = hda_get_stream_by_offsets(offset, HDAC_SDCTL0);
1054 + uint32_t value = hda_get_reg_by_offset(sc, offset);
1055 + int err;
1056 +
1057 + DPRINTF("stream_ind: 0x%x old: 0x%x value: 0x%x\n", stream_ind, old, value);
1058 +
1059 + if (value & HDAC_SDCTL_SRST) {
1060 + hda_stream_reset(sc, stream_ind);
1061 + }
1062 +
1063 + if ((value & HDAC_SDCTL_RUN) != (old & HDAC_SDCTL_RUN)) {
1064 + if (value & HDAC_SDCTL_RUN) {
1065 + err = hda_stream_start(sc, stream_ind);
1066 + assert(!err);
1067 + } else {
1068 + err = hda_stream_stop(sc, stream_ind);
1069 + assert(!err);
1070 + }
1071 + }
1072 +
1073 + return;
1074 +}
1075 +
1076 +static void
1077 +hda_set_sdctl2(struct hda_softc *sc, uint32_t offset, uint32_t old)
1078 +{
1079 + uint32_t value = hda_get_reg_by_offset(sc, offset);
1080 +
1081 + hda_set_field_by_offset(sc, offset - 2, 0x00ff0000, value << 16);
1082 +
1083 + return;
1084 +}
1085 +
1086 +static void
1087 +hda_set_sdsts(struct hda_softc *sc, uint32_t offset, uint32_t old)
1088 +{
1089 + uint32_t value = hda_get_reg_by_offset(sc, offset);
1090 +
1091 + hda_set_reg_by_offset(sc, offset, old);
1092 +
1093 + /* clear the corresponding bits written by the software (guest) */
1094 + hda_set_field_by_offset(sc, offset, value & HDA_SDSTS_IRQ_MASK, 0);
1095 +
1096 + hda_update_intr(sc);
1097 +
1098 + return;
1099 +}
1100 +
1101 +static int
1102 +hda_signal_state_change(struct hda_codec_inst *hci)
1103 +{
1104 + struct hda_softc *sc = NULL;
1105 + uint32_t sdiwake = 0;
1106 +
1107 + assert(hci);
1108 + assert(hci->hda);
1109 +
1110 + DPRINTF("cad: 0x%x\n", hci->cad);
1111 +
1112 + sc = hci->hda;
1113 + sdiwake = 1 << hci->cad;
1114 +
1115 + hda_set_field_by_offset(sc, HDAC_STATESTS, sdiwake, sdiwake);
1116 + hda_update_intr(sc);
1117 +
1118 + return 0;
1119 +}
1120 +
1121 +static int
1122 +hda_response(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol)
1123 +{
1124 + struct hda_softc *sc = NULL;
1125 + struct hda_codec_cmd_ctl *rirb = NULL;
1126 + uint32_t response_ex = 0;
1127 + uint8_t rintcnt = 0;
1128 +
1129 + assert(hci);
1130 + assert(hci->cad <= HDA_CODEC_MAX);
1131 +
1132 + response_ex = hci->cad | unsol;
1133 +
1134 + sc = hci->hda;
1135 + assert(sc);
1136 +
1137 + rirb = &sc->rirb;
1138 +
1139 + if (rirb->run) {
1140 + rirb->wp++;
1141 + rirb->wp %= rirb->size;
1142 +
1143 + hda_dma_st_dword(rirb->dma_vaddr + HDA_RIRB_ENTRY_LEN * rirb->wp, response);
1144 + hda_dma_st_dword(rirb->dma_vaddr + HDA_RIRB_ENTRY_LEN * rirb->wp + 0x04, response_ex);
1145 +
1146 + hda_set_reg_by_offset(sc, HDAC_RIRBWP, rirb->wp);
1147 +
1148 + sc->rirb_cnt++;
1149 + }
1150 +
1151 + rintcnt = hda_get_reg_by_offset(sc, HDAC_RINTCNT);
1152 + if (sc->rirb_cnt == rintcnt)
1153 + hda_response_interrupt(sc);
1154 +
1155 + return 0;
1156 +}
1157 +
1158 +static int
1159 +hda_transfer(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir, void *buf, size_t count)
1160 +{
1161 + struct hda_softc *sc = NULL;
1162 + struct hda_stream_desc *st = NULL;
1163 + struct hda_bdle_desc *bdl = NULL;
1164 + struct hda_bdle_desc *bdle_desc = NULL;
1165 + uint8_t stream_ind = 0;
1166 + uint32_t lpib = 0;
1167 + uint32_t off = 0;
1168 + size_t left = 0;
1169 + uint8_t irq = 0;
1170 +
1171 + assert(hci);
1172 + assert(hci->hda);
1173 + assert(buf);
1174 + assert(!(count % HDA_DMA_ACCESS_LEN));
1175 +
1176 + if (!stream) {
1177 + DPRINTF("Invalid stream\n");
1178 + return -1;
1179 + }
1180 +
1181 + sc = hci->hda;
1182 +
1183 + assert(stream < HDA_STREAM_TAGS_CNT);
1184 + stream_ind = sc->stream_map[dir][stream];
1185 +
1186 + if (!dir)
1187 + assert(stream_ind < HDA_ISS_NO);
1188 + else
1189 + assert(stream_ind >= HDA_ISS_NO && stream_ind < HDA_IOSS_NO);
1190 +
1191 + st = &sc->streams[stream_ind];
1192 + if (!st->run) {
1193 + DPRINTF("Stream 0x%x stopped\n", stream);
1194 + return -1;
1195 + }
1196 +
1197 + assert(st->stream == stream);
1198 +
1199 + off = hda_get_offset_stream(stream_ind);
1200 +
1201 + lpib = hda_get_reg_by_offset(sc, off + HDAC_SDLPIB);
1202 +
1203 + bdl = st->bdl;
1204 +
1205 + assert(st->be < st->bdl_cnt);
1206 + assert(st->bp < bdl[st->be].len);
1207 +
1208 + left = count;
1209 + while (left) {
1210 + bdle_desc = &bdl[st->be];
1211 +
1212 + if (dir)
1213 + *(uint32_t *)buf = hda_dma_ld_dword(bdle_desc->addr + st->bp);
1214 + else
1215 + hda_dma_st_dword(bdle_desc->addr + st->bp, *(uint32_t *)buf);
1216 +
1217 + buf += HDA_DMA_ACCESS_LEN;
1218 + st->bp += HDA_DMA_ACCESS_LEN;
1219 + lpib += HDA_DMA_ACCESS_LEN;
1220 + left -= HDA_DMA_ACCESS_LEN;
1221 +
1222 + if (st->bp == bdle_desc->len) {
1223 + st->bp = 0;
1224 + if (bdle_desc->ioc)
1225 + irq = 1;
1226 + st->be++;
1227 + if (st->be == st->bdl_cnt) {
1228 + st->be = 0;
1229 + lpib = 0;
1230 + }
1231 + bdle_desc = &bdl[st->be];
1232 + }
1233 + }
1234 +
1235 + hda_set_pib(sc, stream_ind, lpib);
1236 +
1237 + if (irq) {
1238 + hda_set_field_by_offset(sc, off + HDAC_SDSTS, HDAC_SDSTS_BCIS, HDAC_SDSTS_BCIS);
1239 + hda_update_intr(sc);
1240 + }
1241 +
1242 + return 0;
1243 +}
1244 +
1245 +static void
1246 +hda_set_pib(struct hda_softc *sc, uint8_t stream_ind, uint32_t pib)
1247 +{
1248 + uint32_t off = hda_get_offset_stream(stream_ind);
1249 +
1250 + hda_set_reg_by_offset(sc, off + HDAC_SDLPIB, pib);
1251 + hda_set_reg_by_offset(sc, 0x2000 + off + HDAC_SDLPIB, pib); /* LPIB Alias */
1252 + if (sc->dma_pib_vaddr)
1253 + *(uint32_t *)(sc->dma_pib_vaddr + stream_ind * HDA_DMA_PIB_ENTRY_LEN) = pib;
1254 +
1255 + return;
1256 +}
1257 +
1258 +static uint64_t hda_get_clock_ns(void)
1259 +{
1260 + struct timespec ts;
1261 + int err;
1262 +
1263 + err = clock_gettime(CLOCK_MONOTONIC, &ts);
1264 + assert(!err);
1265 +
1266 + return ts.tv_sec * 1000000000LL + ts.tv_nsec;
1267 +}
1268 +
1269 +/*
1270 + * PCI HDA function definitions
1271 + */
1272 +static int
1273 +pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1274 +{
1275 + struct hda_softc *sc = NULL;
1276 +
1277 + assert(ctx != NULL);
1278 + assert(pi != NULL);
1279 +
1280 + pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
1281 + pci_set_cfgdata16(pi, PCIR_DEVICE, HDA_INTEL_82801G);
1282 +
1283 + pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_MULTIMEDIA_HDA);
1284 + pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_MULTIMEDIA);
1285 +
1286 + /* select the Intel HDA mode */
1287 + pci_set_cfgdata8(pi, PCIR_HDCTL, 0x01);
1288 +
1289 + /* allocate one BAR register for the Memory address offsets */
1290 + pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, HDA_LAST_OFFSET);
1291 +
1292 + /* allocate an IRQ pin for our slot */
1293 + pci_lintr_request(pi);
1294 +
1295 + sc = hda_init(opts);
1296 + if (!sc)
1297 + return -1;
1298 +
1299 + sc->pci_dev = pi;
1300 + pi->pi_arg = sc;
1301 +
1302 + return 0;
1303 +}
1304 +
1305 +static void
1306 +pci_hda_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1307 + int baridx, uint64_t offset, int size, uint64_t value)
1308 +{
1309 + struct hda_softc *sc = pi->pi_arg;
1310 + int err;
1311 +
1312 + assert(sc);
1313 + assert(baridx == 0);
1314 + assert(size <= 4);
1315 +
1316 + DPRINTF("offset: 0x%lx value: 0x%lx\n", offset, value);
1317 +
1318 + err = hda_write(sc, offset, size, value);
1319 + assert(!err);
1320 +
1321 + return;
1322 +}
1323 +
1324 +static uint64_t
1325 +pci_hda_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1326 + int baridx, uint64_t offset, int size)
1327 +{
1328 + struct hda_softc *sc = pi->pi_arg;
1329 + uint64_t value = 0;
1330 +
1331 + assert(sc);
1332 + assert(baridx == 0);
1333 + assert(size <= 4);
1334 +
1335 + value = hda_read(sc, offset);
1336 +
1337 + DPRINTF("offset: 0x%lx value: 0x%lx\n", offset, value);
1338 +
1339 + return value;
1340 +}
1341 +
1342 +
1343 Index: hda_codec.c
1344 ===================================================================
1345 --- hda_codec.c (revision 0)
1346 +++ hda_codec.c (revision 307412)
1347 @@ -0,0 +1,868 @@
1348 +
1349 +#include <pthread.h>
1350 +#include <pthread_np.h>
1351 +#include <unistd.h>
1352 +
1353 +#include "pci_hda.h"
1354 +#include "audio.h"
1355 +
1356 +/*
1357 + * HDA Codec defines
1358 + */
1359 +#define INTEL_VENDORID 0x8086
1360 +
1361 +#define HDA_CODEC_SUBSYSTEM_ID ((INTEL_VENDORID << 16) | 0x01)
1362 +#define HDA_CODEC_ROOT_NID 0x00
1363 +#define HDA_CODEC_FG_NID 0x01
1364 +#define HDA_CODEC_AUDIO_OUTPUT_NID 0x02
1365 +#define HDA_CODEC_PIN_OUTPUT_NID 0x03
1366 +#define HDA_CODEC_AUDIO_INPUT_NID 0x04
1367 +#define HDA_CODEC_PIN_INPUT_NID 0x05
1368 +
1369 +#define HDA_CODEC_STREAMS_COUNT 0x02
1370 +#define HDA_CODEC_STREAM_OUTPUT 0x00
1371 +#define HDA_CODEC_STREAM_INPUT 0x01
1372 +
1373 +#define HDA_CODEC_PARAMS_COUNT 0x14
1374 +#define HDA_CODEC_CONN_LIST_COUNT 0x01
1375 +#define HDA_CODEC_RESPONSE_EX_UNSOL 0x10
1376 +#define HDA_CODEC_RESPONSE_EX_SOL 0x00
1377 +#define HDA_CODEC_AMP_NUMSTEPS 0x4a
1378 +
1379 +#define HDA_CODEC_SUPP_STREAM_FORMATS_PCM (1 << HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT)
1380 +
1381 +#define HDA_CODEC_FMT_BASE_MASK (0x01 << 14)
1382 +
1383 +#define HDA_CODEC_FMT_MULT_MASK (0x07 << 11)
1384 +#define HDA_CODEC_FMT_MULT_2 (0x01 << 11)
1385 +#define HDA_CODEC_FMT_MULT_3 (0x02 << 11)
1386 +#define HDA_CODEC_FMT_MULT_4 (0x03 << 11)
1387 +
1388 +#define HDA_CODEC_FMT_DIV_MASK 0x07
1389 +#define HDA_CODEC_FMT_DIV_SHIFT 8
1390 +
1391 +#define HDA_CODEC_FMT_BITS_MASK (0x07 << 4)
1392 +#define HDA_CODEC_FMT_BITS_8 (0x00 << 4)
1393 +#define HDA_CODEC_FMT_BITS_16 (0x01 << 4)
1394 +#define HDA_CODEC_FMT_BITS_24 (0x03 << 4)
1395 +#define HDA_CODEC_FMT_BITS_32 (0x04 << 4)
1396 +
1397 +#define HDA_CODEC_FMT_CHAN_MASK (0x0f << 0)
1398 +
1399 +#define HDA_CODEC_AUDIO_WCAP_OUTPUT (0x00 << HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
1400 +#define HDA_CODEC_AUDIO_WCAP_INPUT (0x01 << HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
1401 +#define HDA_CODEC_AUDIO_WCAP_PIN (0x04 << HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
1402 +#define HDA_CODEC_AUDIO_WCAP_CONN_LIST (1 << HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT)
1403 +#define HDA_CODEC_AUDIO_WCAP_FORMAT_OVR (1 << HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT)
1404 +#define HDA_CODEC_AUDIO_WCAP_AMP_OVR (1 << HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT)
1405 +#define HDA_CODEC_AUDIO_WCAP_OUT_AMP (1 << HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT)
1406 +#define HDA_CODEC_AUDIO_WCAP_IN_AMP (1 << HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT)
1407 +#define HDA_CODEC_AUDIO_WCAP_STEREO (1 << HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)
1408 +
1409 +#define HDA_CODEC_PIN_CAP_OUTPUT (1 << HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT)
1410 +#define HDA_CODEC_PIN_CAP_INPUT (1 << HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT)
1411 +#define HDA_CODEC_PIN_CAP_PRESENCE_DETECT (1 << HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT)
1412 +
1413 +#define HDA_CODEC_OUTPUT_AMP_CAP_MUTE_CAP (1 << HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT)
1414 +#define HDA_CODEC_OUTPUT_AMP_CAP_STEPSIZE (0x03 << HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT)
1415 +#define HDA_CODEC_OUTPUT_AMP_CAP_NUMSTEPS (HDA_CODEC_AMP_NUMSTEPS << HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT)
1416 +#define HDA_CODEC_OUTPUT_AMP_CAP_OFFSET (HDA_CODEC_AMP_NUMSTEPS << HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT)
1417 +
1418 +#define HDA_CODEC_SET_AMP_GAIN_MUTE_MUTE 0x80
1419 +#define HDA_CODEC_SET_AMP_GAIN_MUTE_GAIN_MASK 0x7f
1420 +
1421 +#define HDA_CODEC_PIN_SENSE_PRESENCE_PLUGGED (1 << 31)
1422 +#define HDA_CODEC_PIN_WIDGET_CTRL_OUT_ENABLE (1 << HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT)
1423 +#define HDA_CODEC_PIN_WIDGET_CTRL_IN_ENABLE (1 << HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT)
1424 +
1425 +#define HDA_CONFIG_DEFAULTCONF_COLOR_BLACK (0x01 << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
1426 +#define HDA_CONFIG_DEFAULTCONF_COLOR_RED (0x05 << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
1427 +
1428 +#define HDA_CODEC_BUF_SIZE HDA_FIFO_SIZE
1429 +
1430 +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
1431 +
1432 +
1433 +/*
1434 + * HDA Audio Context data structures
1435 + */
1436 +
1437 +typedef void (*transfer_func_t)(void *arg);
1438 +typedef int (*setup_func_t)(void *arg);
1439 +
1440 +struct hda_audio_ctxt {
1441 + uint8_t started;
1442 + char name[64];
1443 + uint8_t run;
1444 + pthread_t tid;
1445 + pthread_mutex_t mtx;
1446 + pthread_cond_t cond;
1447 + transfer_func_t do_transfer;
1448 + setup_func_t do_setup;
1449 + void *priv;
1450 +};
1451 +
1452 +/*
1453 + * HDA Audio Context module function declarations
1454 + */
1455 +
1456 +static void *
1457 +hda_audio_ctxt_thr(void *arg);
1458 +static int
1459 +hda_audio_ctxt_init(struct hda_audio_ctxt *actx, const char *tname, transfer_func_t do_transfer, setup_func_t do_setup, void *priv);
1460 +static int
1461 +hda_audio_ctxt_start(struct hda_audio_ctxt *actx);
1462 +static int
1463 +hda_audio_ctxt_stop(struct hda_audio_ctxt *actx);
1464 +
1465 +/*
1466 + * HDA Codec data structures
1467 + */
1468 +
1469 +struct hda_codec_softc;
1470 +
1471 +typedef uint32_t (*verb_func_t)(struct hda_codec_softc *sc, uint16_t verb, uint16_t payload);
1472 +
1473 +struct hda_codec_stream {
1474 + uint8_t buf[HDA_CODEC_BUF_SIZE];
1475 + uint8_t stream;
1476 + uint8_t channel;
1477 + uint16_t fmt;
1478 +
1479 + uint8_t left_gain;
1480 + uint8_t right_gain;
1481 + uint8_t left_mute;
1482 + uint8_t right_mute;
1483 +
1484 + struct hda_audio_ctxt actx;
1485 + struct audio *aud;
1486 +};
1487 +
1488 +struct hda_codec_softc {
1489 + struct hda_codec_inst *hci;
1490 + uint32_t subsystem_id;
1491 + uint32_t no_nodes;
1492 + const uint32_t (*get_parameters)[HDA_CODEC_PARAMS_COUNT];
1493 + const uint8_t (*conn_list)[HDA_CODEC_CONN_LIST_COUNT];
1494 + const uint32_t *conf_default;
1495 + const uint8_t *pin_ctrl_default;
1496 + const verb_func_t *verb_handlers;
1497 +
1498 + struct hda_codec_stream streams[HDA_CODEC_STREAMS_COUNT];
1499 +};
1500 +
1501 +/*
1502 + * HDA Codec module function declarations
1503 + */
1504 +static int
1505 +hda_codec_init(struct hda_codec_inst *hci, const char *play, const char *rec, const char *opts);
1506 +static int
1507 +hda_codec_reset(struct hda_codec_inst *hci);
1508 +static int
1509 +hda_codec_command(struct hda_codec_inst *hci, uint32_t cmd_data);
1510 +static int
1511 +hda_codec_notify(struct hda_codec_inst *hci, uint8_t run, uint8_t stream, uint8_t dir);
1512 +
1513 +static int hda_codec_parse_format(uint16_t fmt, struct audio_params *params);
1514 +
1515 +static uint32_t
1516 +hda_codec_audio_output_nid(struct hda_codec_softc *sc, uint16_t verb, uint16_t payload);
1517 +static void
1518 +hda_codec_audio_output_do_transfer(void *arg);
1519 +static int
1520 +hda_codec_audio_output_do_setup(void *arg);
1521 +static uint32_t
1522 +hda_codec_audio_input_nid(struct hda_codec_softc *sc, uint16_t verb, uint16_t payload);
1523 +static void
1524 +hda_codec_audio_input_do_transfer(void *arg);
1525 +static int
1526 +hda_codec_audio_input_do_setup(void *arg);
1527 +
1528 +static uint32_t
1529 +hda_codec_audio_inout_nid(struct hda_codec_stream *st, uint16_t verb, uint16_t payload);
1530 +
1531 +/*
1532 + * HDA Codec global data
1533 + */
1534 +
1535 +#define HDA_CODEC_ROOT_DESC \
1536 + [HDA_CODEC_ROOT_NID] = { \
1537 + [HDA_PARAM_VENDOR_ID] = INTEL_VENDORID, \
1538 + [HDA_PARAM_REVISION_ID] = 0xffff, \
1539 + [HDA_PARAM_SUB_NODE_COUNT] = 0x00010001, /* 1 Subnode, StartNid = 1 */ \
1540 + }, \
1541 +
1542 +#define HDA_CODEC_FG_COMMON_DESC \
1543 + [HDA_PARAM_FCT_GRP_TYPE] = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO, \
1544 + [HDA_PARAM_SUPP_PCM_SIZE_RATE] = (0x1f << 16) | 0x7ff, /* B8 - B32, 8.0 - 192.0kHz */ \
1545 + [HDA_PARAM_SUPP_STREAM_FORMATS] = HDA_CODEC_SUPP_STREAM_FORMATS_PCM, \
1546 + [HDA_PARAM_INPUT_AMP_CAP] = 0x00, /* None */ \
1547 + [HDA_PARAM_OUTPUT_AMP_CAP] = 0x00, /* None */ \
1548 + [HDA_PARAM_GPIO_COUNT] = 0x00, \
1549 +
1550 +#define HDA_CODEC_FG_OUTPUT_DESC \
1551 + [HDA_CODEC_FG_NID] = { \
1552 + [HDA_PARAM_SUB_NODE_COUNT] = 0x00020002, /* 2 Subnodes, StartNid = 2 */ \
1553 + HDA_CODEC_FG_COMMON_DESC \
1554 + }, \
1555 +
1556 +#define HDA_CODEC_FG_INPUT_DESC \
1557 + [HDA_CODEC_FG_NID] = { \
1558 + [HDA_PARAM_SUB_NODE_COUNT] = 0x00040002, /* 2 Subnodes, StartNid = 4 */ \
1559 + HDA_CODEC_FG_COMMON_DESC \
1560 + }, \
1561 +
1562 +#define HDA_CODEC_FG_DUPLEX_DESC \
1563 + [HDA_CODEC_FG_NID] = { \
1564 + [HDA_PARAM_SUB_NODE_COUNT] = 0x00020004, /* 4 Subnodes, StartNid = 2 */ \
1565 + HDA_CODEC_FG_COMMON_DESC \
1566 + }, \
1567 +
1568 +#define HDA_CODEC_OUTPUT_DESC \
1569 + [HDA_CODEC_AUDIO_OUTPUT_NID] = { \
1570 + [HDA_PARAM_AUDIO_WIDGET_CAP] = HDA_CODEC_AUDIO_WCAP_OUTPUT | \
1571 + HDA_CODEC_AUDIO_WCAP_FORMAT_OVR | \
1572 + HDA_CODEC_AUDIO_WCAP_AMP_OVR | \
1573 + HDA_CODEC_AUDIO_WCAP_OUT_AMP | \
1574 + HDA_CODEC_AUDIO_WCAP_STEREO, \
1575 + [HDA_PARAM_SUPP_PCM_SIZE_RATE] = (0x02 << 16) | 0x7fc, /* B16, 16.0 - 192.0kHz */ \
1576 + [HDA_PARAM_SUPP_STREAM_FORMATS] = HDA_CODEC_SUPP_STREAM_FORMATS_PCM, \
1577 + [HDA_PARAM_INPUT_AMP_CAP] = 0x00, /* None */ \
1578 + [HDA_PARAM_CONN_LIST_LENGTH] = 0x00, \
1579 + [HDA_PARAM_OUTPUT_AMP_CAP] = HDA_CODEC_OUTPUT_AMP_CAP_MUTE_CAP | \
1580 + HDA_CODEC_OUTPUT_AMP_CAP_STEPSIZE | \
1581 + HDA_CODEC_OUTPUT_AMP_CAP_NUMSTEPS | \
1582 + HDA_CODEC_OUTPUT_AMP_CAP_OFFSET, \
1583 + }, \
1584 + [HDA_CODEC_PIN_OUTPUT_NID] = { \
1585 + [HDA_PARAM_AUDIO_WIDGET_CAP] = HDA_CODEC_AUDIO_WCAP_PIN | \
1586 + HDA_CODEC_AUDIO_WCAP_CONN_LIST | \
1587 + HDA_CODEC_AUDIO_WCAP_STEREO, \
1588 + [HDA_PARAM_PIN_CAP] = HDA_CODEC_PIN_CAP_OUTPUT | \
1589 + HDA_CODEC_PIN_CAP_PRESENCE_DETECT, \
1590 + [HDA_PARAM_INPUT_AMP_CAP] = 0x00, /* None */ \
1591 + [HDA_PARAM_CONN_LIST_LENGTH] = 0x01, \
1592 + [HDA_PARAM_OUTPUT_AMP_CAP] = 0x00, /* None */ \
1593 + }, \
1594 +
1595 +#define HDA_CODEC_INPUT_DESC \
1596 + [HDA_CODEC_AUDIO_INPUT_NID] = { \
1597 + [HDA_PARAM_AUDIO_WIDGET_CAP] = HDA_CODEC_AUDIO_WCAP_INPUT | \
1598 + HDA_CODEC_AUDIO_WCAP_CONN_LIST | \
1599 + HDA_CODEC_AUDIO_WCAP_FORMAT_OVR | \
1600 + HDA_CODEC_AUDIO_WCAP_AMP_OVR | \
1601 + HDA_CODEC_AUDIO_WCAP_IN_AMP | \
1602 + HDA_CODEC_AUDIO_WCAP_STEREO, \
1603 + [HDA_PARAM_SUPP_PCM_SIZE_RATE] = (0x02 << 16) | 0x7fc, /* B16, 16.0 - 192.0kHz */ \
1604 + [HDA_PARAM_SUPP_STREAM_FORMATS] = HDA_CODEC_SUPP_STREAM_FORMATS_PCM, \
1605 + [HDA_PARAM_OUTPUT_AMP_CAP] = 0x00, /* None */ \
1606 + [HDA_PARAM_CONN_LIST_LENGTH] = 0x01, \
1607 + [HDA_PARAM_INPUT_AMP_CAP] = HDA_CODEC_OUTPUT_AMP_CAP_MUTE_CAP | \
1608 + HDA_CODEC_OUTPUT_AMP_CAP_STEPSIZE | \
1609 + HDA_CODEC_OUTPUT_AMP_CAP_NUMSTEPS | \
1610 + HDA_CODEC_OUTPUT_AMP_CAP_OFFSET, \
1611 + }, \
1612 + [HDA_CODEC_PIN_INPUT_NID] = { \
1613 + [HDA_PARAM_AUDIO_WIDGET_CAP] = HDA_CODEC_AUDIO_WCAP_PIN | \
1614 + HDA_CODEC_AUDIO_WCAP_STEREO, \
1615 + [HDA_PARAM_PIN_CAP] = HDA_CODEC_PIN_CAP_INPUT | \
1616 + HDA_CODEC_PIN_CAP_PRESENCE_DETECT, \
1617 + [HDA_PARAM_INPUT_AMP_CAP] = 0x00, /* None */ \
1618 + [HDA_PARAM_OUTPUT_AMP_CAP] = 0x00, /* None */ \
1619 + }, \
1620 +
1621 +static const uint32_t hda_codec_output_parameters[][HDA_CODEC_PARAMS_COUNT] = {
1622 + HDA_CODEC_ROOT_DESC
1623 + HDA_CODEC_FG_OUTPUT_DESC
1624 + HDA_CODEC_OUTPUT_DESC
1625 +};
1626 +
1627 +static const uint32_t hda_codec_input_parameters[][HDA_CODEC_PARAMS_COUNT] = {
1628 + HDA_CODEC_ROOT_DESC
1629 + HDA_CODEC_FG_INPUT_DESC
1630 + HDA_CODEC_INPUT_DESC
1631 +};
1632 +
1633 +static const uint32_t hda_codec_duplex_parameters[][HDA_CODEC_PARAMS_COUNT] = {
1634 + HDA_CODEC_ROOT_DESC
1635 + HDA_CODEC_FG_DUPLEX_DESC
1636 + HDA_CODEC_OUTPUT_DESC
1637 + HDA_CODEC_INPUT_DESC
1638 +};
1639 +
1640 +#define HDA_CODEC_NODES_COUNT (ARRAY_SIZE(hda_codec_duplex_parameters))
1641 +
1642 +static const uint8_t hda_codec_conn_list[HDA_CODEC_NODES_COUNT][HDA_CODEC_CONN_LIST_COUNT] = {
1643 + [HDA_CODEC_PIN_OUTPUT_NID] = {HDA_CODEC_AUDIO_OUTPUT_NID},
1644 + [HDA_CODEC_AUDIO_INPUT_NID] = {HDA_CODEC_PIN_INPUT_NID},
1645 +};
1646 +
1647 +static const uint32_t hda_codec_conf_default[HDA_CODEC_NODES_COUNT] = {
1648 + [HDA_CODEC_PIN_OUTPUT_NID] = HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK |
1649 + HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
1650 + HDA_CONFIG_DEFAULTCONF_COLOR_BLACK |
1651 + (0x01 << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT),
1652 + [HDA_CODEC_PIN_INPUT_NID] = HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK |
1653 + HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN |
1654 + HDA_CONFIG_DEFAULTCONF_COLOR_RED |
1655 + (0x02 << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT),
1656 +};
1657 +
1658 +static const uint8_t hda_codec_pin_ctrl_default[HDA_CODEC_NODES_COUNT] = {
1659 + [HDA_CODEC_PIN_OUTPUT_NID] = HDA_CODEC_PIN_WIDGET_CTRL_OUT_ENABLE,
1660 + [HDA_CODEC_PIN_INPUT_NID] = HDA_CODEC_PIN_WIDGET_CTRL_IN_ENABLE,
1661 +};
1662 +
1663 +static const verb_func_t hda_codec_verb_handlers[HDA_CODEC_NODES_COUNT] = {
1664 + [HDA_CODEC_AUDIO_OUTPUT_NID] = hda_codec_audio_output_nid,
1665 + [HDA_CODEC_AUDIO_INPUT_NID] = hda_codec_audio_input_nid,
1666 +};
1667 +
1668 +/*
1669 + * HDA Codec module function definitions
1670 + */
1671 +
1672 +static int
1673 +hda_codec_init(struct hda_codec_inst *hci, const char *play, const char *rec, const char *opts)
1674 +{
1675 + struct hda_codec_softc *sc = NULL;
1676 + struct hda_codec_stream *st = NULL;
1677 + int err;
1678 +
1679 + if (!(play || rec))
1680 + return -1;
1681 +
1682 + DPRINTF("cad: 0x%x opts: %s\n", hci->cad, opts);
1683 +
1684 + sc = calloc(1, sizeof(*sc));
1685 + if (!sc)
1686 + return -1;
1687 +
1688 + if (play && rec)
1689 + sc->get_parameters = hda_codec_duplex_parameters;
1690 + else {
1691 + if (play)
1692 + sc->get_parameters = hda_codec_output_parameters;
1693 + else
1694 + sc->get_parameters = hda_codec_input_parameters;
1695 + }
1696 + sc->subsystem_id = HDA_CODEC_SUBSYSTEM_ID;
1697 + sc->no_nodes = HDA_CODEC_NODES_COUNT;
1698 + sc->conn_list = hda_codec_conn_list;
1699 + sc->conf_default = hda_codec_conf_default;
1700 + sc->pin_ctrl_default = hda_codec_pin_ctrl_default;
1701 + sc->verb_handlers = hda_codec_verb_handlers;
1702 + DPRINTF("HDA Codec nodes: %d\n", sc->no_nodes);
1703 +
1704 + /*
1705 + * Initialize the Audio Output stream
1706 + */
1707 + if (play) {
1708 + st = &sc->streams[HDA_CODEC_STREAM_OUTPUT];
1709 +
1710 + err = hda_audio_ctxt_init(&st->actx, "hda-audio-output",
1711 + hda_codec_audio_output_do_transfer, hda_codec_audio_output_do_setup, sc);
1712 + assert(!err);
1713 +
1714 + st->aud = audio_init(play, 1);
1715 + if (!st->aud) {
1716 + DPRINTF("Fail to init the output audio player\n");
1717 + return -1;
1718 + }
1719 + }
1720 +
1721 + /*
1722 + * Initialize the Audio Input stream
1723 + */
1724 + if (rec) {
1725 + st = &sc->streams[HDA_CODEC_STREAM_INPUT];
1726 +
1727 + err = hda_audio_ctxt_init(&st->actx, "hda-audio-input",
1728 + hda_codec_audio_input_do_transfer, hda_codec_audio_input_do_setup, sc);
1729 + assert(!err);
1730 +
1731 + st->aud = audio_init(rec, 0);
1732 + if (!st->aud) {
1733 + DPRINTF("Fail to init the input audio player\n");
1734 + return -1;
1735 + }
1736 + }
1737 +
1738 + sc->hci = hci;
1739 + hci->priv = sc;
1740 +
1741 + return 0;
1742 +}
1743 +
1744 +static int
1745 +hda_codec_reset(struct hda_codec_inst *hci)
1746 +{
1747 + struct hda_ops *hops = NULL;
1748 + struct hda_codec_softc *sc = NULL;
1749 + struct hda_codec_stream *st = NULL;
1750 + int i;
1751 +
1752 + assert(hci);
1753 +
1754 + hops = hci->hops;
1755 + assert(hops);
1756 +
1757 + sc = (struct hda_codec_softc *)hci->priv;
1758 + assert(sc);
1759 +
1760 + for (i = 0; i < HDA_CODEC_STREAMS_COUNT; i++) {
1761 + st = &sc->streams[i];
1762 + st->left_gain = HDA_CODEC_AMP_NUMSTEPS;
1763 + st->right_gain = HDA_CODEC_AMP_NUMSTEPS;
1764 + st->left_mute = HDA_CODEC_SET_AMP_GAIN_MUTE_MUTE;
1765 + st->right_mute = HDA_CODEC_SET_AMP_GAIN_MUTE_MUTE;
1766 + }
1767 +
1768 + DPRINTF("cad: 0x%x\n", hci->cad);
1769 +
1770 + if (!hops->signal) {
1771 + DPRINTF("The controller ops does not implement the signal function\n");
1772 + return -1;
1773 + }
1774 +
1775 + return hops->signal(hci);
1776 +}
1777 +
1778 +static int
1779 +hda_codec_command(struct hda_codec_inst *hci, uint32_t cmd_data)
1780 +{
1781 + struct hda_codec_softc *sc = NULL;
1782 + struct hda_ops *hops = NULL;
1783 + uint8_t cad = 0, nid = 0;
1784 + uint16_t verb = 0, payload = 0;
1785 + uint32_t res = 0;
1786 +
1787 + cad = (cmd_data >> HDA_CMD_CAD_SHIFT) & 0x0f; // 4 bits
1788 + nid = (cmd_data >> HDA_CMD_NID_SHIFT) & 0xff; // 8 bits
1789 +
1790 + if ((cmd_data & 0x70000) == 0x70000) {
1791 + verb = (cmd_data >> HDA_CMD_VERB_12BIT_SHIFT) & 0x0fff; // 12 bits
1792 + payload = cmd_data & 0xff; // 8 bits
1793 + } else {
1794 + verb = (cmd_data >> HDA_CMD_VERB_4BIT_SHIFT) & 0x0f; // 4 bits
1795 + payload = cmd_data & 0xffff; // 16 bits
1796 + }
1797 +
1798 + assert(cad == hci->cad);
1799 + assert(hci);
1800 +
1801 + hops = hci->hops;
1802 + assert(hops);
1803 +
1804 + sc = (struct hda_codec_softc *)hci->priv;
1805 + assert(sc);
1806 +
1807 + assert(nid < sc->no_nodes);
1808 +
1809 + if (!hops->response) {
1810 + DPRINTF("The controller ops does not implement the response function\n");
1811 + return -1;
1812 + }
1813 +
1814 + switch (verb) {
1815 + case HDA_CMD_VERB_GET_PARAMETER:
1816 + res = sc->get_parameters[nid][payload];
1817 + break;
1818 + case HDA_CMD_VERB_GET_CONN_LIST_ENTRY:
1819 + res = sc->conn_list[nid][0];
1820 + break;
1821 + case HDA_CMD_VERB_GET_PIN_WIDGET_CTRL:
1822 + res = sc->pin_ctrl_default[nid];
1823 + break;
1824 + case HDA_CMD_VERB_GET_PIN_SENSE:
1825 + res = HDA_CODEC_PIN_SENSE_PRESENCE_PLUGGED;
1826 + break;
1827 + case HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT:
1828 + res = sc->conf_default[nid];
1829 + break;
1830 + case HDA_CMD_VERB_GET_SUBSYSTEM_ID:
1831 + res = sc->subsystem_id;
1832 + break;
1833 + default:
1834 + assert(sc->verb_handlers);
1835 + if (sc->verb_handlers[nid])
1836 + res = sc->verb_handlers[nid](sc, verb, payload);
1837 + else
1838 + DPRINTF("Unknown VERB: 0x%x\n", verb);
1839 + break;
1840 + }
1841 +
1842 + DPRINTF("cad: 0x%x nid: 0x%x verb: 0x%x payload: 0x%x response: 0x%x\n",
1843 + cad, nid, verb, payload, res);
1844 +
1845 + return hops->response(hci, res, HDA_CODEC_RESPONSE_EX_SOL);
1846 +}
1847 +
1848 +static int
1849 +hda_codec_notify(struct hda_codec_inst *hci, uint8_t run, uint8_t stream, uint8_t dir)
1850 +{
1851 + struct hda_codec_softc *sc = NULL;
1852 + struct hda_codec_stream *st = NULL;
1853 + struct hda_audio_ctxt *actx = NULL;
1854 + int i;
1855 + int err;
1856 +
1857 + assert(hci);
1858 + assert(stream);
1859 +
1860 + sc = (struct hda_codec_softc *)hci->priv;
1861 + assert(sc);
1862 +
1863 + i = dir ? HDA_CODEC_STREAM_OUTPUT : HDA_CODEC_STREAM_INPUT;
1864 + st = &sc->streams[i];
1865 +
1866 + DPRINTF("run: %d, stream: 0x%x, st->stream: 0x%x dir: %d\n", run, stream, st->stream, dir);
1867 +
1868 + if (stream != st->stream) {
1869 + DPRINTF("Stream not found\n");
1870 + return 0;
1871 + }
1872 +
1873 + actx = &st->actx;
1874 +
1875 + if (run)
1876 + err = hda_audio_ctxt_start(actx);
1877 + else
1878 + err = hda_audio_ctxt_stop(actx);
1879 +
1880 + return err;
1881 +}
1882 +
1883 +static int hda_codec_parse_format(uint16_t fmt, struct audio_params *params)
1884 +{
1885 + uint8_t div = 0;
1886 +
1887 + assert(params);
1888 +
1889 + /* Compute the Sample Rate */
1890 + params->rate = (fmt & HDA_CODEC_FMT_BASE_MASK) ? 44100 : 48000;
1891 +
1892 + switch (fmt & HDA_CODEC_FMT_MULT_MASK) {
1893 + case HDA_CODEC_FMT_MULT_2:
1894 + params->rate *= 2;
1895 + break;
1896 + case HDA_CODEC_FMT_MULT_3:
1897 + params->rate *= 3;
1898 + break;
1899 + case HDA_CODEC_FMT_MULT_4:
1900 + params->rate *= 4;
1901 + break;
1902 + }
1903 +
1904 + div = (fmt >> HDA_CODEC_FMT_DIV_SHIFT) & HDA_CODEC_FMT_DIV_MASK;
1905 + params->rate /= (div + 1);
1906 +
1907 + /* Compute the Bits per Sample */
1908 + switch (fmt & HDA_CODEC_FMT_BITS_MASK) {
1909 + case HDA_CODEC_FMT_BITS_8:
1910 + params->format = AFMT_U8;
1911 + break;
1912 + case HDA_CODEC_FMT_BITS_16:
1913 + params->format = AFMT_S16_LE;
1914 + break;
1915 + case HDA_CODEC_FMT_BITS_24:
1916 + params->format = AFMT_S24_LE;
1917 + break;
1918 + case HDA_CODEC_FMT_BITS_32:
1919 + params->format = AFMT_S32_LE;
1920 + break;
1921 + default:
1922 + DPRINTF("Unknown format bits: 0x%x\n", fmt & HDA_CODEC_FMT_BITS_MASK);
1923 + return -1;
1924 + }
1925 +
1926 + /* Compute the Number of Channels */
1927 + params->channels = (fmt & HDA_CODEC_FMT_CHAN_MASK) + 1;
1928 +
1929 + return 0;
1930 +}
1931 +
1932 +static uint32_t
1933 +hda_codec_audio_output_nid(struct hda_codec_softc *sc, uint16_t verb, uint16_t payload)
1934 +{
1935 + struct hda_codec_stream *st = &sc->streams[HDA_CODEC_STREAM_OUTPUT];
1936 + int res;
1937 +
1938 + res = hda_codec_audio_inout_nid(st, verb, payload);
1939 +
1940 + return res;
1941 +}
1942 +
1943 +static void
1944 +hda_codec_audio_output_do_transfer(void *arg)
1945 +{
1946 + struct hda_codec_softc *sc = (struct hda_codec_softc *)arg;
1947 + struct hda_codec_inst *hci = NULL;
1948 + struct hda_ops *hops = NULL;
1949 + struct hda_codec_stream *st = NULL;
1950 + struct audio *aud = NULL;
1951 + int err;
1952 +
1953 + hci = sc->hci;
1954 + assert(hci);
1955 +
1956 + hops = hci->hops;
1957 + assert(hops);
1958 +
1959 + st = &sc->streams[HDA_CODEC_STREAM_OUTPUT];
1960 + aud = st->aud;
1961 +
1962 + err = hops->transfer(hci, st->stream, 1, st->buf, sizeof(st->buf));
1963 + if (err)
1964 + return;
1965 +
1966 + err = audio_playback(aud, st->buf, sizeof(st->buf));
1967 + assert(!err);
1968 +
1969 + return;
1970 +}
1971 +
1972 +static int
1973 +hda_codec_audio_output_do_setup(void *arg)
1974 +{
1975 + struct hda_codec_softc *sc = (struct hda_codec_softc *)arg;
1976 + struct hda_codec_stream *st = NULL;
1977 + struct audio *aud = NULL;
1978 + struct audio_params params;
1979 + int err;
1980 +
1981 + st = &sc->streams[HDA_CODEC_STREAM_OUTPUT];
1982 + aud = st->aud;
1983 +
1984 + err = hda_codec_parse_format(st->fmt, ¶ms);
1985 + if (err)
1986 + return -1;
1987 +
1988 + DPRINTF("rate: %d, channels: %d, format: 0x%x\n", params.rate, params.channels, params.format);
1989 +
1990 + return audio_set_params(aud, ¶ms);
1991 +}
1992 +
1993 +static uint32_t
1994 +hda_codec_audio_input_nid(struct hda_codec_softc *sc, uint16_t verb, uint16_t payload)
1995 +{
1996 + struct hda_codec_stream *st = &sc->streams[HDA_CODEC_STREAM_INPUT];
1997 + int res;
1998 +
1999 + res = hda_codec_audio_inout_nid(st, verb, payload);
2000 +
2001 + return res;
2002 +}
2003 +
2004 +static void
2005 +hda_codec_audio_input_do_transfer(void *arg)
2006 +{
2007 + struct hda_codec_softc *sc = (struct hda_codec_softc *)arg;
2008 + struct hda_codec_inst *hci = NULL;
2009 + struct hda_ops *hops = NULL;
2010 + struct hda_codec_stream *st = NULL;
2011 + struct audio *aud = NULL;
2012 + int err;
2013 +
2014 + hci = sc->hci;
2015 + assert(hci);
2016 +
2017 + hops = hci->hops;
2018 + assert(hops);
2019 +
2020 + st = &sc->streams[HDA_CODEC_STREAM_INPUT];
2021 + aud = st->aud;
2022 +
2023 + err = audio_record(aud, st->buf, sizeof(st->buf));
2024 + assert(!err);
2025 +
2026 + hops->transfer(hci, st->stream, 0, st->buf, sizeof(st->buf));
2027 +
2028 + return;
2029 +}
2030 +
2031 +static int
2032 +hda_codec_audio_input_do_setup(void *arg)
2033 +{
2034 + struct hda_codec_softc *sc = (struct hda_codec_softc *)arg;
2035 + struct hda_codec_stream *st = NULL;
2036 + struct audio *aud = NULL;
2037 + struct audio_params params;
2038 + int err;
2039 +
2040 + st = &sc->streams[HDA_CODEC_STREAM_INPUT];
2041 + aud = st->aud;
2042 +
2043 + err = hda_codec_parse_format(st->fmt, ¶ms);
2044 + if (err)
2045 + return -1;
2046 +
2047 + DPRINTF("rate: %d, channels: %d, format: 0x%x\n", params.rate, params.channels, params.format);
2048 +
2049 + return audio_set_params(aud, ¶ms);
2050 +}
2051 +
2052 +static uint32_t
2053 +hda_codec_audio_inout_nid(struct hda_codec_stream *st, uint16_t verb, uint16_t payload)
2054 +{
2055 + uint32_t res = 0;
2056 + uint8_t mute = 0;
2057 + uint8_t gain = 0;
2058 +
2059 + DPRINTF("%s verb: 0x%x, payload, 0x%x\n", st->actx.name, verb, payload);
2060 +
2061 + switch (verb) {
2062 + case HDA_CMD_VERB_GET_CONV_FMT:
2063 + res = st->fmt;
2064 + break;
2065 + case HDA_CMD_VERB_SET_CONV_FMT:
2066 + st->fmt = payload;
2067 + break;
2068 + case HDA_CMD_VERB_GET_AMP_GAIN_MUTE:
2069 + if (payload & HDA_CMD_GET_AMP_GAIN_MUTE_LEFT) {
2070 + res = st->left_gain | st->left_mute;
2071 + DPRINTF("GET_AMP_GAIN_MUTE_LEFT: 0x%x\n", res);
2072 + } else {
2073 + res = st->right_gain | st->right_mute;
2074 + DPRINTF("GET_AMP_GAIN_MUTE_RIGHT: 0x%x\n", res);
2075 + }
2076 + break;
2077 + case HDA_CMD_VERB_SET_AMP_GAIN_MUTE:
2078 + mute = payload & HDA_CODEC_SET_AMP_GAIN_MUTE_MUTE;
2079 + gain = payload & HDA_CODEC_SET_AMP_GAIN_MUTE_GAIN_MASK;
2080 +
2081 + if (payload & HDA_CMD_SET_AMP_GAIN_MUTE_LEFT) {
2082 + st->left_mute = mute;
2083 + st->left_gain = gain;
2084 + DPRINTF("SET_AMP_GAIN_MUTE_LEFT: mute: 0x%x gain: 0x%x\n", mute, gain);
2085 + }
2086 +
2087 + if (payload & HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT) {
2088 + st->right_mute = mute;
2089 + st->right_gain = gain;
2090 + DPRINTF("SET_AMP_GAIN_MUTE_RIGHT: mute: 0x%x gain: 0x%x\n", mute, gain);
2091 + }
2092 + break;
2093 + case HDA_CMD_VERB_GET_CONV_STREAM_CHAN:
2094 + res = (st->stream << 4) | st->channel;
2095 + break;
2096 + case HDA_CMD_VERB_SET_CONV_STREAM_CHAN:
2097 + st->channel = payload & 0x0f;
2098 + st->stream = (payload >> 4) & 0x0f;
2099 + DPRINTF("st->channel: 0x%x st->stream: 0x%x\n", st->channel, st->stream);
2100 + if (!st->stream)
2101 + hda_audio_ctxt_stop(&st->actx);
2102 + break;
2103 + default:
2104 + DPRINTF("Unknown VERB: 0x%x\n", verb);
2105 + break;
2106 + }
2107 +
2108 + return res;
2109 +}
2110 +
2111 +struct hda_codec_class hda_codec = {
2112 + .name = "hda_codec",
2113 + .init = hda_codec_init,
2114 + .reset = hda_codec_reset,
2115 + .command = hda_codec_command,
2116 + .notify = hda_codec_notify,
2117 +};
2118 +
2119 +HDA_EMUL_SET(hda_codec);
2120 +
2121 +
2122 +/*
2123 + * HDA Audio Context module function definitions
2124 + */
2125 +
2126 +static void *
2127 +hda_audio_ctxt_thr(void *arg)
2128 +{
2129 + struct hda_audio_ctxt *actx = (struct hda_audio_ctxt *)arg;
2130 +
2131 + DPRINTF("Start Thread: %s\n", actx->name);
2132 +
2133 + pthread_mutex_lock(&actx->mtx);
2134 + while (1) {
2135 + while (!actx->run)
2136 + pthread_cond_wait(&actx->cond, &actx->mtx);
2137 +
2138 + actx->do_transfer(actx->priv);
2139 + }
2140 + pthread_mutex_unlock(&actx->mtx);
2141 +
2142 + pthread_exit(NULL);
2143 +
2144 + return NULL;
2145 +}
2146 +
2147 +static int
2148 +hda_audio_ctxt_init(struct hda_audio_ctxt *actx, const char *tname, transfer_func_t do_transfer, setup_func_t do_setup, void *priv)
2149 +{
2150 + int err;
2151 +
2152 + assert(actx);
2153 + assert(tname);
2154 + assert(do_transfer);
2155 + assert(do_setup);
2156 + assert(priv);
2157 +
2158 + memset(actx, 0, sizeof(*actx));
2159 +
2160 + actx->run = 0;
2161 + actx->do_transfer = do_transfer;
2162 + actx->do_setup = do_setup;
2163 + actx->priv = priv;
2164 + if (strlen(tname) < sizeof(actx->name))
2165 + memcpy(actx->name, tname, strlen(tname) + 1);
2166 + else
2167 + strcpy(actx->name, "unknown");
2168 +
2169 + err = pthread_mutex_init(&actx->mtx, NULL);
2170 + assert(!err);
2171 +
2172 + err = pthread_cond_init(&actx->cond, NULL);
2173 + assert(!err);
2174 +
2175 + err = pthread_create(&actx->tid, NULL, hda_audio_ctxt_thr, actx);
2176 + assert(!err);
2177 +
2178 + pthread_set_name_np(actx->tid, tname);
2179 + assert(!err);
2180 +
2181 + actx->started = 1;
2182 +
2183 + return 0;
2184 +}
2185 +
2186 +static int
2187 +hda_audio_ctxt_start(struct hda_audio_ctxt *actx)
2188 +{
2189 + int err = 0;
2190 +
2191 + assert(actx);
2192 + assert(actx->started);
2193 +
2194 + /* The stream is supposed to be stopped */
2195 + if (actx->run)
2196 + return -1;
2197 +
2198 + pthread_mutex_lock(&actx->mtx);
2199 + err = actx->do_setup(actx->priv);
2200 + if (!err) {
2201 + actx->run = 1;
2202 + pthread_cond_signal(&actx->cond);
2203 + }
2204 + pthread_mutex_unlock(&actx->mtx);
2205 +
2206 + return err;
2207 +}
2208 +
2209 +static int
2210 +hda_audio_ctxt_stop(struct hda_audio_ctxt *actx)
2211 +{
2212 + actx->run = 0;
2213 + return 0;
2214 +}
2215 +
2216 Index: pci_hda.h
2217 ===================================================================
2218 --- pci_hda.h (revision 0)
2219 +++ pci_hda.h (revision 307412)
2220 @@ -0,0 +1,59 @@
2221 +
2222 +#ifndef _HDA_EMUL_H_
2223 +#define _HDA_EMUL_H_
2224 +
2225 +#include <stdio.h>
2226 +#include <stdlib.h>
2227 +#include <string.h>
2228 +#include <sys/types.h>
2229 +#include <assert.h>
2230 +
2231 +#include <sys/types.h>
2232 +#include <sys/queue.h>
2233 +#include <sys/kernel.h>
2234 +
2235 +#include "hda_reg.h"
2236 +
2237 +/*
2238 + * HDA Debug Log
2239 + */
2240 +#define DEBUG_HDA 1
2241 +#if DEBUG_HDA == 1
2242 +extern FILE *dbg;
2243 +#define DPRINTF(fmt, arg...) \
2244 +do {fprintf(dbg, "%s-%d: " fmt, __func__, __LINE__, ##arg); \
2245 +fflush(dbg); } while (0)
2246 +#else
2247 +#define DPRINTF(fmt, arg...)
2248 +#endif
2249 +
2250 +#define HDA_FIFO_SIZE 0x100
2251 +
2252 +struct hda_softc;
2253 +struct hda_codec_class;
2254 +
2255 +struct hda_codec_inst {
2256 + struct hda_codec_class *codec;
2257 + struct hda_softc *hda;
2258 + struct hda_ops *hops;
2259 + uint8_t cad;
2260 + void *priv;
2261 +};
2262 +
2263 +struct hda_codec_class {
2264 + char *name;
2265 + int (*init)(struct hda_codec_inst *hci, const char *play, const char *rec, const char *opts);
2266 + int (*reset)(struct hda_codec_inst *hci);
2267 + int (*command)(struct hda_codec_inst *hci, uint32_t cmd_data);
2268 + int (*notify)(struct hda_codec_inst *hci, uint8_t run, uint8_t stream, uint8_t dir);
2269 +};
2270 +
2271 +struct hda_ops {
2272 + int (*signal)(struct hda_codec_inst *hci);
2273 + int (*response)(struct hda_codec_inst *hci, uint32_t response, uint8_t unsol);
2274 + int (*transfer)(struct hda_codec_inst *hci, uint8_t stream, uint8_t dir, void *buf, size_t count);
2275 +};
2276 +
2277 +#define HDA_EMUL_SET(x) DATA_SET(hda_codec_class_set, x);
2278 +
2279 +#endif /* _HDA_EMUL_H_ */
2280 Index: audio.c
2281 ===================================================================
2282 --- audio.c (revision 0)
2283 +++ audio.c (revision 307412)
2284 @@ -0,0 +1,207 @@
2285 +
2286 +#include <stdio.h>
2287 +#include <stdlib.h>
2288 +#include <fcntl.h>
2289 +#include <sys/ioctl.h>
2290 +#include <unistd.h>
2291 +#include <assert.h>
2292 +#include <errno.h>
2293 +
2294 +#include "audio.h"
2295 +#include "pci_hda.h"
2296 +
2297 +/*
2298 + * Audio Player internal data structures
2299 + */
2300 +
2301 +struct audio {
2302 + int fd;
2303 + uint8_t dir;
2304 + char dev_name[64];
2305 +};
2306 +
2307 +/*
2308 + * Audio Player module function definitions
2309 + */
2310 +
2311 +/*
2312 + * audio_init - initialize an instance of audio player
2313 + * @dev_name - the backend sound device used to play / capture
2314 + * @dir - dir = 1 for write mode, dir = 0 for read mode
2315 + */
2316 +struct audio *audio_init(const char *dev_name, uint8_t dir)
2317 +{
2318 + struct audio *aud = NULL;
2319 +
2320 + assert(dev_name);
2321 +
2322 + aud = calloc(1, sizeof(*aud));
2323 + if (!aud)
2324 + return NULL;
2325 +
2326 + if (strlen(dev_name) < sizeof(aud->dev_name))
2327 + memcpy(aud->dev_name, dev_name, strlen(dev_name) + 1);
2328 + else {
2329 + DPRINTF("dev_name too big\n");
2330 + free(aud);
2331 + return NULL;
2332 + }
2333 +
2334 + aud->fd = -1;
2335 + aud->dir = dir;
2336 +
2337 + return aud;
2338 +}
2339 +
2340 +/*
2341 + * audio_set_params - reset the sound device and set the audio params
2342 + * @aud - the audio player to be configured
2343 + * @params - the audio parameters to be set
2344 + */
2345 +int audio_set_params(struct audio *aud, struct audio_params *params)
2346 +{
2347 + int audio_fd = -1;
2348 + int format, channels, rate;
2349 + int err;
2350 +#if DEBUG_HDA == 1
2351 + audio_buf_info info;
2352 +#endif
2353 +
2354 + assert(aud);
2355 + assert(params);
2356 +
2357 + /* Close the device if was opened before */
2358 + if (aud->fd != -1) {
2359 + err = close(aud->fd);
2360 + if (err == -1) {
2361 + DPRINTF("Fail to close fd: %d, errno: %d\n", aud->fd, errno);
2362 + return -1;
2363 + }
2364 + }
2365 +
2366 + audio_fd = open(aud->dev_name, aud->dir ? O_WRONLY : O_RDONLY, 0);
2367 + if (audio_fd == -1) {
2368 + DPRINTF("Fail to open dev: %s, errno: %d\n", aud->dev_name, errno);
2369 + return -1;
2370 + }
2371 +
2372 + aud->fd = audio_fd;
2373 +
2374 + /* Set the Format (Bits per Sample) */
2375 + format = params->format;
2376 + err = ioctl(audio_fd, SNDCTL_DSP_SETFMT, &format);
2377 + if (err == -1) {
2378 + DPRINTF("Fail to set fmt: 0x%x errno: %d\n", params->format, errno);
2379 + return -1;
2380 + }
2381 +
2382 + /* The device does not support the requested audio format */
2383 + if (format != params->format) {
2384 + DPRINTF("Mismatch format: 0x%x params->format: 0x%x\n", format, params->format);
2385 + return -1;
2386 + }
2387 +
2388 + /* Set the Number of Channels */
2389 + channels = params->channels;
2390 + err = ioctl(audio_fd, SNDCTL_DSP_CHANNELS, &channels);
2391 + if (err == -1) {
2392 + DPRINTF("Fail to set channels: %d errno: %d\n", params->channels, errno);
2393 + return -1;
2394 + }
2395 +
2396 + /* The device does not support the requested no. of channels */
2397 + if (channels != params->channels) {
2398 + DPRINTF("Mismatch channels: %d params->channels: %d\n", channels, params->channels);
2399 + return -1;
2400 + }
2401 +
2402 + /* Set the Sample Rate / Speed */
2403 + rate = params->rate;
2404 + err = ioctl(audio_fd, SNDCTL_DSP_SPEED, &rate);
2405 + if (err == -1) {
2406 + DPRINTF("Fail to set speed: %d errno: %d\n", params->rate, errno);
2407 + return -1;
2408 + }
2409 +
2410 + /* The device does not support the requested rate / speed */
2411 + if (rate != params->rate) {
2412 + DPRINTF("Mismatch rate: %d params->rate: %d\n", rate, params->rate);
2413 + return -1;
2414 + }
2415 +
2416 +#if DEBUG_HDA == 1
2417 + err = ioctl(audio_fd, aud->dir ? SNDCTL_DSP_GETOSPACE : SNDCTL_DSP_GETISPACE, &info);
2418 + if (err == -1) {
2419 + DPRINTF("Fail to get audio buf info errno: %d\n", errno);
2420 + return -1;
2421 + }
2422 + DPRINTF("fragstotal: 0x%x fragsize: 0x%x\n", info.fragstotal, info.fragsize);
2423 +#endif
2424 + return 0;
2425 +}
2426 +
2427 +/*
2428 + * audio_playback - plays samples to the sound device using blocking operations
2429 + * @aud - the audio player used to play the samples
2430 + * @buf - the buffer containing the samples
2431 + * @count - the number of bytes in buffer
2432 + */
2433 +int audio_playback(struct audio *aud, const void *buf, size_t count)
2434 +{
2435 + int audio_fd = -1;
2436 + ssize_t len = 0, total = 0;
2437 +
2438 + assert(aud);
2439 + assert(aud->dir);
2440 + assert(buf);
2441 +
2442 + audio_fd = aud->fd;
2443 + assert(audio_fd != -1);
2444 +
2445 + total = 0;
2446 + while (total < count) {
2447 + len = write(audio_fd, buf + total, count - total);
2448 + if (len == -1) {
2449 + DPRINTF("Fail to write to fd: %d, errno: %d\n", audio_fd, errno);
2450 + return -1;
2451 + }
2452 +
2453 + total += len;
2454 + }
2455 +
2456 + return 0;
2457 +}
2458 +
2459 +/*
2460 + * audio_record - records samples from the sound device using blocking operations
2461 + * @aud - the audio player used to capture the samples
2462 + * @buf - the buffer to receive the samples
2463 + * @count - the number of bytes to capture in buffer
2464 + * Returns -1 on error and 0 on success
2465 + */
2466 +int audio_record(struct audio *aud, void *buf, size_t count)
2467 +{
2468 + int audio_fd = -1;
2469 + ssize_t len = 0, total = 0;
2470 +
2471 + assert(aud);
2472 + assert(!aud->dir);
2473 + assert(buf);
2474 +
2475 + audio_fd = aud->fd;
2476 + assert(audio_fd != -1);
2477 +
2478 + total = 0;
2479 + while (total < count) {
2480 + len = read(audio_fd, buf + total, count - total);
2481 + if (len == -1) {
2482 + DPRINTF("Fail to write to fd: %d, errno: %d\n", audio_fd, errno);
2483 + return -1;
2484 + }
2485 +
2486 + total += len;
2487 + }
2488 +
2489 + return 0;
2490 +}
2491 +
2492 Index: audio.h
2493 ===================================================================
2494 --- audio.h (revision 0)
2495 +++ audio.h (revision 307412)
2496 @@ -0,0 +1,58 @@
2497 +
2498 +#ifndef _AUDIO_EMUL_H_
2499 +#define _AUDIO_EMUL_H_
2500 +
2501 +#include <sys/types.h>
2502 +#include <sys/soundcard.h>
2503 +
2504 +/*
2505 + * Audio Player data structures
2506 + */
2507 +
2508 +struct audio;
2509 +
2510 +struct audio_params {
2511 + int format;
2512 + int channels;
2513 + int rate;
2514 +};
2515 +
2516 +/*
2517 + * Audio Player API
2518 + */
2519 +
2520 +/*
2521 + * audio_init - initialize an instance of audio player
2522 + * @dev_name - the backend sound device used to play / capture
2523 + * @dir - dir = 1 for write mode, dir = 0 for read mode
2524 + * Returns NULL on error and the address of the audio player instance
2525 + */
2526 +struct audio *audio_init(const char *dev_name, uint8_t dir);
2527 +
2528 +/*
2529 + * audio_set_params - reset the sound device and set the audio params
2530 + * @aud - the audio player to be configured
2531 + * @params - the audio parameters to be set
2532 + * Returns -1 on error and 0 on success
2533 + */
2534 +int audio_set_params(struct audio *aud, struct audio_params *params);
2535 +
2536 +/*
2537 + * audio_playback - plays samples to the sound device using blocking operations
2538 + * @aud - the audio player used to play the samples
2539 + * @buf - the buffer containing the samples
2540 + * @count - the number of bytes in buffer
2541 + * Returns -1 on error and 0 on success
2542 + */
2543 +int audio_playback(struct audio *aud, const void *buf, size_t count);
2544 +
2545 +/*
2546 + * audio_record - records samples from the sound device using blocking operations
2547 + * @aud - the audio player used to capture the samples
2548 + * @buf - the buffer to receive the samples
2549 + * @count - the number of bytes to capture in buffer
2550 + * Returns -1 on error and 0 on success
2551 + */
2552 +int audio_record(struct audio *aud, void *buf, size_t count);
2553 +
2554 +#endif /* _AUDIO_EMUL_H_ */
2555 Index: Makefile
2556 ===================================================================
2557 --- Makefile (revision 302727)
2558 +++ Makefile (revision 307412)
2559 @@ -14,12 +14,14 @@
2560 SRCS= \
2561 atkbdc.c \
2562 acpi.c \
2563 + audio.c \
2564 bhyverun.c \
2565 block_if.c \
2566 bootrom.c \
2567 consport.c \
2568 dbgport.c \
2569 fwctl.c \
2570 + hda_codec.c \
2571 inout.c \
2572 ioapic.c \
2573 mem.c \
2574 @@ -27,6 +29,7 @@
2575 mptbl.c \
2576 pci_ahci.c \
2577 pci_emul.c \
2578 + pci_hda.c \
2579 pci_hostbridge.c \
2580 pci_irq.c \
2581 pci_lpc.c \
2582 Index: hda_reg.h
2583 ===================================================================
2584 --- hda_reg.h (revision 0)
2585 +++ hda_reg.h (revision 307412)
2586 @@ -0,0 +1,1367 @@
2587 +/*-
2588 + * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
2589 + * All rights reserved.
2590 + *
2591 + * Redistribution and use in source and binary forms, with or without
2592 + * modification, are permitted provided that the following conditions
2593 + * are met:
2594 + * 1. Redistributions of source code must retain the above copyright
2595 + * notice, this list of conditions and the following disclaimer.
2596 + * 2. Redistributions in binary form must reproduce the above copyright
2597 + * notice, this list of conditions and the following disclaimer in the
2598 + * documentation and/or other materials provided with the distribution.
2599 + *
2600 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
2601 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2602 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2603 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
2604 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
2605 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2606 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2607 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2608 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2609 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2610 + * SUCH DAMAGE.
2611 + *
2612 + * $FreeBSD$
2613 + */
2614 +
2615 +#ifndef _HDA_REG_H_
2616 +#define _HDA_REG_H_
2617 +
2618 +/****************************************************************************
2619 + * HDA Device Verbs
2620 + ****************************************************************************/
2621 +
2622 +/* HDA Command */
2623 +#define HDA_CMD_VERB_MASK 0x000fffff
2624 +#define HDA_CMD_VERB_SHIFT 0
2625 +#define HDA_CMD_NID_MASK 0x0ff00000
2626 +#define HDA_CMD_NID_SHIFT 20
2627 +#define HDA_CMD_CAD_MASK 0xf0000000
2628 +#define HDA_CMD_CAD_SHIFT 28
2629 +
2630 +#define HDA_CMD_VERB_4BIT_SHIFT 16
2631 +#define HDA_CMD_VERB_12BIT_SHIFT 8
2632 +
2633 +#define HDA_CMD_VERB_4BIT(verb, payload) \
2634 + (((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload))
2635 +#define HDA_CMD_4BIT(cad, nid, verb, payload) \
2636 + (((cad) << HDA_CMD_CAD_SHIFT) | \
2637 + ((nid) << HDA_CMD_NID_SHIFT) | \
2638 + (HDA_CMD_VERB_4BIT((verb), (payload))))
2639 +
2640 +#define HDA_CMD_VERB_12BIT(verb, payload) \
2641 + (((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload))
2642 +#define HDA_CMD_12BIT(cad, nid, verb, payload) \
2643 + (((cad) << HDA_CMD_CAD_SHIFT) | \
2644 + ((nid) << HDA_CMD_NID_SHIFT) | \
2645 + (HDA_CMD_VERB_12BIT((verb), (payload))))
2646 +
2647 +/* Get Parameter */
2648 +#define HDA_CMD_VERB_GET_PARAMETER 0xf00
2649 +
2650 +#define HDA_CMD_GET_PARAMETER(cad, nid, payload) \
2651 + (HDA_CMD_12BIT((cad), (nid), \
2652 + HDA_CMD_VERB_GET_PARAMETER, (payload)))
2653 +
2654 +/* Connection Select Control */
2655 +#define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
2656 +#define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
2657 +
2658 +#define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \
2659 + (HDA_CMD_12BIT((cad), (nid), \
2660 + HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
2661 +#define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \
2662 + (HDA_CMD_12BIT((cad), (nid), \
2663 + HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload)))
2664 +
2665 +/* Connection List Entry */
2666 +#define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
2667 +
2668 +#define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \
2669 + (HDA_CMD_12BIT((cad), (nid), \
2670 + HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload)))
2671 +
2672 +#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1
2673 +#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2
2674 +
2675 +/* Processing State */
2676 +#define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
2677 +#define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703
2678 +
2679 +#define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \
2680 + (HDA_CMD_12BIT((cad), (nid), \
2681 + HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0))
2682 +#define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \
2683 + (HDA_CMD_12BIT((cad), (nid), \
2684 + HDA_CMD_VERB_SET_PROCESSING_STATE, (payload)))
2685 +
2686 +#define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00
2687 +#define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01
2688 +#define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02
2689 +
2690 +/* Coefficient Index */
2691 +#define HDA_CMD_VERB_GET_COEFF_INDEX 0xd
2692 +#define HDA_CMD_VERB_SET_COEFF_INDEX 0x5
2693 +
2694 +#define HDA_CMD_GET_COEFF_INDEX(cad, nid) \
2695 + (HDA_CMD_4BIT((cad), (nid), \
2696 + HDA_CMD_VERB_GET_COEFF_INDEX, 0x0))
2697 +#define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \
2698 + (HDA_CMD_4BIT((cad), (nid), \
2699 + HDA_CMD_VERB_SET_COEFF_INDEX, (payload)))
2700 +
2701 +/* Processing Coefficient */
2702 +#define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc
2703 +#define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4
2704 +
2705 +#define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \
2706 + (HDA_CMD_4BIT((cad), (nid), \
2707 + HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0))
2708 +#define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \
2709 + (HDA_CMD_4BIT((cad), (nid), \
2710 + HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload)))
2711 +
2712 +/* Amplifier Gain/Mute */
2713 +#define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb
2714 +#define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3
2715 +
2716 +#define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \
2717 + (HDA_CMD_4BIT((cad), (nid), \
2718 + HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload)))
2719 +#define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \
2720 + (HDA_CMD_4BIT((cad), (nid), \
2721 + HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload)))
2722 +
2723 +#define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000
2724 +#define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000
2725 +#define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000
2726 +#define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000
2727 +
2728 +#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008
2729 +#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7
2730 +#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007
2731 +#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0
2732 +
2733 +#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \
2734 + (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \
2735 + HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT)
2736 +#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \
2737 + (((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \
2738 + HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT)
2739 +
2740 +#define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000
2741 +#define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000
2742 +#define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000
2743 +#define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000
2744 +#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00
2745 +#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8
2746 +#define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080
2747 +#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007
2748 +#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0
2749 +
2750 +#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \
2751 + (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \
2752 + HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK)
2753 +#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \
2754 + (((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \
2755 + HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK)
2756 +
2757 +/* Converter format */
2758 +#define HDA_CMD_VERB_GET_CONV_FMT 0xa
2759 +#define HDA_CMD_VERB_SET_CONV_FMT 0x2
2760 +
2761 +#define HDA_CMD_GET_CONV_FMT(cad, nid) \
2762 + (HDA_CMD_4BIT((cad), (nid), \
2763 + HDA_CMD_VERB_GET_CONV_FMT, 0x0))
2764 +#define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \
2765 + (HDA_CMD_4BIT((cad), (nid), \
2766 + HDA_CMD_VERB_SET_CONV_FMT, (payload)))
2767 +
2768 +/* Digital Converter Control */
2769 +#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d
2770 +#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e
2771 +#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d
2772 +#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e
2773 +
2774 +#define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \
2775 + (HDA_CMD_12BIT((cad), (nid), \
2776 + HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0))
2777 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \
2778 + (HDA_CMD_12BIT((cad), (nid), \
2779 + HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload)))
2780 +#define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \
2781 + (HDA_CMD_12BIT((cad), (nid), \
2782 + HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload)))
2783 +
2784 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00
2785 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8
2786 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080
2787 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7
2788 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040
2789 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6
2790 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020
2791 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5
2792 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010
2793 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4
2794 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008
2795 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3
2796 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004
2797 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2
2798 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002
2799 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1
2800 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001
2801 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0
2802 +
2803 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \
2804 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \
2805 + HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT)
2806 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \
2807 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \
2808 + HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT)
2809 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \
2810 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \
2811 + HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT)
2812 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \
2813 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \
2814 + HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT)
2815 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \
2816 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \
2817 + HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT)
2818 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \
2819 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \
2820 + HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT)
2821 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \
2822 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \
2823 + HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT)
2824 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \
2825 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \
2826 + HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT)
2827 +#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \
2828 + (((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \
2829 + HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT)
2830 +
2831 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80
2832 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40
2833 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20
2834 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10
2835 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08
2836 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04
2837 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02
2838 +#define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01
2839 +
2840 +/* Power State */
2841 +#define HDA_CMD_VERB_GET_POWER_STATE 0xf05
2842 +#define HDA_CMD_VERB_SET_POWER_STATE 0x705
2843 +
2844 +#define HDA_CMD_GET_POWER_STATE(cad, nid) \
2845 + (HDA_CMD_12BIT((cad), (nid), \
2846 + HDA_CMD_VERB_GET_POWER_STATE, 0x0))
2847 +#define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \
2848 + (HDA_CMD_12BIT((cad), (nid), \
2849 + HDA_CMD_VERB_SET_POWER_STATE, (payload)))
2850 +
2851 +#define HDA_CMD_POWER_STATE_D0 0x00
2852 +#define HDA_CMD_POWER_STATE_D1 0x01
2853 +#define HDA_CMD_POWER_STATE_D2 0x02
2854 +#define HDA_CMD_POWER_STATE_D3 0x03
2855 +
2856 +#define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0
2857 +#define HDA_CMD_POWER_STATE_ACT_SHIFT 4
2858 +#define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f
2859 +#define HDA_CMD_POWER_STATE_SET_SHIFT 0
2860 +
2861 +#define HDA_CMD_GET_POWER_STATE_ACT(rsp) \
2862 + (((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \
2863 + HDA_CMD_POWER_STATE_ACT_SHIFT)
2864 +#define HDA_CMD_GET_POWER_STATE_SET(rsp) \
2865 + (((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \
2866 + HDA_CMD_POWER_STATE_SET_SHIFT)
2867 +
2868 +#define HDA_CMD_SET_POWER_STATE_ACT(ps) \
2869 + (((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \
2870 + HDA_CMD_POWER_STATE_ACT_MASK)
2871 +#define HDA_CMD_SET_POWER_STATE_SET(ps) \
2872 + (((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \
2873 + HDA_CMD_POWER_STATE_ACT_MASK)
2874 +
2875 +/* Converter Stream, Channel */
2876 +#define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06
2877 +#define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706
2878 +
2879 +#define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \
2880 + (HDA_CMD_12BIT((cad), (nid), \
2881 + HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0))
2882 +#define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \
2883 + (HDA_CMD_12BIT((cad), (nid), \
2884 + HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload)))
2885 +
2886 +#define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0
2887 +#define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4
2888 +#define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f
2889 +#define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0
2890 +
2891 +#define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \
2892 + (((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \
2893 + HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT)
2894 +#define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \
2895 + (((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \
2896 + HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT)
2897 +
2898 +#define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \
2899 + (((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \
2900 + HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK)
2901 +#define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \
2902 + (((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \
2903 + HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK)
2904 +
2905 +/* Input Converter SDI Select */
2906 +#define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04
2907 +#define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704
2908 +
2909 +#define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \
2910 + (HDA_CMD_12BIT((cad), (nid), \
2911 + HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0))
2912 +#define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \
2913 + (HDA_CMD_12BIT((cad), (nid), \
2914 + HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload)))
2915 +
2916 +/* Pin Widget Control */
2917 +#define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07
2918 +#define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707
2919 +
2920 +#define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \
2921 + (HDA_CMD_12BIT((cad), (nid), \
2922 + HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0))
2923 +#define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \
2924 + (HDA_CMD_12BIT((cad), (nid), \
2925 + HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload)))
2926 +
2927 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080
2928 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7
2929 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040
2930 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6
2931 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020
2932 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5
2933 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007
2934 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
2935 +
2936 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \
2937 + (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \
2938 + HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT)
2939 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \
2940 + (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \
2941 + HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT)
2942 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \
2943 + (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \
2944 + HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT)
2945 +#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \
2946 + (((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \
2947 + HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT)
2948 +
2949 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80
2950 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40
2951 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20
2952 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07
2953 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
2954 +
2955 +#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \
2956 + (((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \
2957 + HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
2958 +
2959 +#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0
2960 +#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1
2961 +#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2
2962 +#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4
2963 +#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5
2964 +
2965 +/* Unsolicited Response */
2966 +#define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08
2967 +#define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708
2968 +
2969 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \
2970 + (HDA_CMD_12BIT((cad), (nid), \
2971 + HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0))
2972 +#define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \
2973 + (HDA_CMD_12BIT((cad), (nid), \
2974 + HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload)))
2975 +
2976 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080
2977 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7
2978 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f
2979 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
2980 +
2981 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \
2982 + (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \
2983 + HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT)
2984 +#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \
2985 + (((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \
2986 + HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT)
2987 +
2988 +#define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80
2989 +#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f
2990 +#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
2991 +
2992 +#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \
2993 + (((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \
2994 + HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK)
2995 +
2996 +/* Pin Sense */
2997 +#define HDA_CMD_VERB_GET_PIN_SENSE 0xf09
2998 +#define HDA_CMD_VERB_SET_PIN_SENSE 0x709
2999 +
3000 +#define HDA_CMD_GET_PIN_SENSE(cad, nid) \
3001 + (HDA_CMD_12BIT((cad), (nid), \
3002 + HDA_CMD_VERB_GET_PIN_SENSE, 0x0))
3003 +#define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \
3004 + (HDA_CMD_12BIT((cad), (nid), \
3005 + HDA_CMD_VERB_SET_PIN_SENSE, (payload)))
3006 +
3007 +#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000
3008 +#define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000
3009 +#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff
3010 +#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0
3011 +
3012 +#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \
3013 + (((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \
3014 + HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT)
3015 +
3016 +#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff
3017 +
3018 +#define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00
3019 +#define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01
3020 +
3021 +/* EAPD/BTL Enable */
3022 +#define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c
3023 +#define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c
3024 +
3025 +#define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \
3026 + (HDA_CMD_12BIT((cad), (nid), \
3027 + HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0))
3028 +#define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \
3029 + (HDA_CMD_12BIT((cad), (nid), \
3030 + HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload)))
3031 +
3032 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004
3033 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2
3034 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002
3035 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1
3036 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001
3037 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0
3038 +
3039 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \
3040 + (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \
3041 + HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT)
3042 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \
3043 + (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \
3044 + HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT)
3045 +#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \
3046 + (((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \
3047 + HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT)
3048 +
3049 +#define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04
3050 +#define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02
3051 +#define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01
3052 +
3053 +/* GPI Data */
3054 +#define HDA_CMD_VERB_GET_GPI_DATA 0xf10
3055 +#define HDA_CMD_VERB_SET_GPI_DATA 0x710
3056 +
3057 +#define HDA_CMD_GET_GPI_DATA(cad, nid) \
3058 + (HDA_CMD_12BIT((cad), (nid), \
3059 + HDA_CMD_VERB_GET_GPI_DATA, 0x0))
3060 +#define HDA_CMD_SET_GPI_DATA(cad, nid) \
3061 + (HDA_CMD_12BIT((cad), (nid), \
3062 + HDA_CMD_VERB_SET_GPI_DATA, (payload)))
3063 +
3064 +/* GPI Wake Enable Mask */
3065 +#define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11
3066 +#define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711
3067 +
3068 +#define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \
3069 + (HDA_CMD_12BIT((cad), (nid), \
3070 + HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0))
3071 +#define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \
3072 + (HDA_CMD_12BIT((cad), (nid), \
3073 + HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload)))
3074 +
3075 +/* GPI Unsolicited Enable Mask */
3076 +#define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12
3077 +#define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712
3078 +
3079 +#define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \
3080 + (HDA_CMD_12BIT((cad), (nid), \
3081 + HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0))
3082 +#define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
3083 + (HDA_CMD_12BIT((cad), (nid), \
3084 + HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload)))
3085 +
3086 +/* GPI Sticky Mask */
3087 +#define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13
3088 +#define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713
3089 +
3090 +#define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \
3091 + (HDA_CMD_12BIT((cad), (nid), \
3092 + HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0))
3093 +#define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \
3094 + (HDA_CMD_12BIT((cad), (nid), \
3095 + HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload)))
3096 +
3097 +/* GPO Data */
3098 +#define HDA_CMD_VERB_GET_GPO_DATA 0xf14
3099 +#define HDA_CMD_VERB_SET_GPO_DATA 0x714
3100 +
3101 +#define HDA_CMD_GET_GPO_DATA(cad, nid) \
3102 + (HDA_CMD_12BIT((cad), (nid), \
3103 + HDA_CMD_VERB_GET_GPO_DATA, 0x0))
3104 +#define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \
3105 + (HDA_CMD_12BIT((cad), (nid), \
3106 + HDA_CMD_VERB_SET_GPO_DATA, (payload)))
3107 +
3108 +/* GPIO Data */
3109 +#define HDA_CMD_VERB_GET_GPIO_DATA 0xf15
3110 +#define HDA_CMD_VERB_SET_GPIO_DATA 0x715
3111 +
3112 +#define HDA_CMD_GET_GPIO_DATA(cad, nid) \
3113 + (HDA_CMD_12BIT((cad), (nid), \
3114 + HDA_CMD_VERB_GET_GPIO_DATA, 0x0))
3115 +#define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \
3116 + (HDA_CMD_12BIT((cad), (nid), \
3117 + HDA_CMD_VERB_SET_GPIO_DATA, (payload)))
3118 +
3119 +/* GPIO Enable Mask */
3120 +#define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16
3121 +#define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716
3122 +
3123 +#define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \
3124 + (HDA_CMD_12BIT((cad), (nid), \
3125 + HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0))
3126 +#define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \
3127 + (HDA_CMD_12BIT((cad), (nid), \
3128 + HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload)))
3129 +
3130 +/* GPIO Direction */
3131 +#define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17
3132 +#define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717
3133 +
3134 +#define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \
3135 + (HDA_CMD_12BIT((cad), (nid), \
3136 + HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0))
3137 +#define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \
3138 + (HDA_CMD_12BIT((cad), (nid), \
3139 + HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload)))
3140 +
3141 +/* GPIO Wake Enable Mask */
3142 +#define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18
3143 +#define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718
3144 +
3145 +#define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \
3146 + (HDA_CMD_12BIT((cad), (nid), \
3147 + HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0))
3148 +#define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \
3149 + (HDA_CMD_12BIT((cad), (nid), \
3150 + HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload)))
3151 +
3152 +/* GPIO Unsolicited Enable Mask */
3153 +#define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19
3154 +#define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719
3155 +
3156 +#define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \
3157 + (HDA_CMD_12BIT((cad), (nid), \
3158 + HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0))
3159 +#define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
3160 + (HDA_CMD_12BIT((cad), (nid), \
3161 + HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload)))
3162 +
3163 +/* GPIO_STICKY_MASK */
3164 +#define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a
3165 +#define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a
3166 +
3167 +#define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \
3168 + (HDA_CMD_12BIT((cad), (nid), \
3169 + HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0))
3170 +#define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \
3171 + (HDA_CMD_12BIT((cad), (nid), \
3172 + HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload)))
3173 +
3174 +/* Beep Generation */
3175 +#define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a
3176 +#define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a
3177 +
3178 +#define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \
3179 + (HDA_CMD_12BIT((cad), (nid), \
3180 + HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0))
3181 +#define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \
3182 + (HDA_CMD_12BIT((cad), (nid), \
3183 + HDA_CMD_VERB_SET_BEEP_GENERATION, (payload)))
3184 +
3185 +/* Volume Knob */
3186 +#define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f
3187 +#define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f
3188 +
3189 +#define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \
3190 + (HDA_CMD_12BIT((cad), (nid), \
3191 + HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0))
3192 +#define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \
3193 + (HDA_CMD_12BIT((cad), (nid), \
3194 + HDA_CMD_VERB_SET_VOLUME_KNOB, (payload)))
3195 +
3196 +/* Subsystem ID */
3197 +#define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20
3198 +#define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720
3199 +#define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721
3200 +#define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722
3201 +#define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723
3202 +
3203 +#define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \
3204 + (HDA_CMD_12BIT((cad), (nid), \
3205 + HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0))
3206 +#define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \
3207 + (HDA_CMD_12BIT((cad), (nid), \
3208 + HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload)))
3209 +#define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \
3210 + (HDA_CMD_12BIT((cad), (nid), \
3211 + HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload)))
3212 +#define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \
3213 + (HDA_CMD_12BIT((cad), (nid), \
3214 + HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload)))
3215 +#define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \
3216 + (HDA_CMD_12BIT((cad), (nid), \
3217 + HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload)))
3218 +
3219 +/* Configuration Default */
3220 +#define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c
3221 +#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c
3222 +#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d
3223 +#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e
3224 +#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f
3225 +
3226 +#define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \
3227 + (HDA_CMD_12BIT((cad), (nid), \
3228 + HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0))
3229 +#define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \
3230 + (HDA_CMD_12BIT((cad), (nid), \
3231 + HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload)))
3232 +#define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \
3233 + (HDA_CMD_12BIT((cad), (nid), \
3234 + HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload)))
3235 +#define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \
3236 + (HDA_CMD_12BIT((cad), (nid), \
3237 + HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload)))
3238 +#define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \
3239 + (HDA_CMD_12BIT((cad), (nid), \
3240 + HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload)))
3241 +
3242 +/* Stripe Control */
3243 +#define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24
3244 +#define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724
3245 +
3246 +#define HDA_CMD_GET_STRIPE_CONTROL(cad, nid) \
3247 + (HDA_CMD_12BIT((cad), (nid), \
3248 + HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0))
3249 +#define HDA_CMD_SET_STRIPE_CONTROL(cad, nid, payload) \
3250 + (HDA_CMD_12BIT((cad), (nid), \
3251 + HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload)))
3252 +
3253 +/* Channel Count Control */
3254 +#define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d
3255 +#define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
3256 +
3257 +#define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \
3258 + (HDA_CMD_12BIT((cad), (nid), \
3259 + HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0))
3260 +#define HDA_CMD_SET_CONV_CHAN_COUNT(cad, nid, payload) \
3261 + (HDA_CMD_12BIT((cad), (nid), \
3262 + HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload)))
3263 +
3264 +#define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
3265 +
3266 +#define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \
3267 + (HDA_CMD_12BIT((cad), (nid), \
3268 + HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg)))
3269 +
3270 +#define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
3271 +
3272 +#define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \
3273 + (HDA_CMD_12BIT((cad), (nid), \
3274 + HDA_CMD_VERB_GET_HDMI_ELDD, (off)))
3275 +
3276 +#define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
3277 +#define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
3278 +
3279 +#define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \
3280 + (HDA_CMD_12BIT((cad), (nid), \
3281 + HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0))
3282 +#define HDA_CMD_SET_HDMI_DIP_INDEX(cad, nid, payload) \
3283 + (HDA_CMD_12BIT((cad), (nid), \
3284 + HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload)))
3285 +
3286 +#define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
3287 +#define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
3288 +
3289 +#define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \
3290 + (HDA_CMD_12BIT((cad), (nid), \
3291 + HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0))
3292 +#define HDA_CMD_SET_HDMI_DIP_DATA(cad, nid, payload) \
3293 + (HDA_CMD_12BIT((cad), (nid), \
3294 + HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload)))
3295 +
3296 +#define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
3297 +#define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
3298 +
3299 +#define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \
3300 + (HDA_CMD_12BIT((cad), (nid), \
3301 + HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0))
3302 +#define HDA_CMD_SET_HDMI_DIP_XMIT(cad, nid, payload) \
3303 + (HDA_CMD_12BIT((cad), (nid), \
3304 + HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload)))
3305 +
3306 +#define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
3307 +#define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
3308 +
3309 +#define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
3310 +#define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
3311 +
3312 +#define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \
3313 + (HDA_CMD_12BIT((cad), (nid), \
3314 + HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0))
3315 +#define HDA_CMD_SET_HDMI_CHAN_SLOT(cad, nid, payload) \
3316 + (HDA_CMD_12BIT((cad), (nid), \
3317 + HDA_CMD_VERB_SET_HDMI_CHAN_SLOT, (payload)))
3318 +
3319 +#define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0
3320 +#define HDA_HDMI_CODING_TYPE_LPCM 1
3321 +#define HDA_HDMI_CODING_TYPE_AC3 2
3322 +#define HDA_HDMI_CODING_TYPE_MPEG1 3
3323 +#define HDA_HDMI_CODING_TYPE_MP3 4
3324 +#define HDA_HDMI_CODING_TYPE_MPEG2 5
3325 +#define HDA_HDMI_CODING_TYPE_AACLC 6
3326 +#define HDA_HDMI_CODING_TYPE_DTS 7
3327 +#define HDA_HDMI_CODING_TYPE_ATRAC 8
3328 +#define HDA_HDMI_CODING_TYPE_SACD 9
3329 +#define HDA_HDMI_CODING_TYPE_EAC3 10
3330 +#define HDA_HDMI_CODING_TYPE_DTS_HD 11
3331 +#define HDA_HDMI_CODING_TYPE_MLP 12
3332 +#define HDA_HDMI_CODING_TYPE_DST 13
3333 +#define HDA_HDMI_CODING_TYPE_WMAPRO 14
3334 +#define HDA_HDMI_CODING_TYPE_REF_CTX 15
3335 +
3336 +/* Function Reset */
3337 +#define HDA_CMD_VERB_FUNCTION_RESET 0x7ff
3338 +
3339 +#define HDA_CMD_FUNCTION_RESET(cad, nid) \
3340 + (HDA_CMD_12BIT((cad), (nid), \
3341 + HDA_CMD_VERB_FUNCTION_RESET, 0x0))
3342 +
3343 +
3344 +/****************************************************************************
3345 + * HDA Device Parameters
3346 + ****************************************************************************/
3347 +
3348 +/* Vendor ID */
3349 +#define HDA_PARAM_VENDOR_ID 0x00
3350 +
3351 +#define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000
3352 +#define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16
3353 +#define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff
3354 +#define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0
3355 +
3356 +#define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \
3357 + (((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \
3358 + HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT)
3359 +#define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \
3360 + (((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \
3361 + HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT)
3362 +
3363 +/* Revision ID */
3364 +#define HDA_PARAM_REVISION_ID 0x02
3365 +
3366 +#define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000
3367 +#define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20
3368 +#define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000
3369 +#define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16
3370 +#define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00
3371 +#define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8
3372 +#define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff
3373 +#define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0
3374 +
3375 +#define HDA_PARAM_REVISION_ID_MAJREV(param) \
3376 + (((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \
3377 + HDA_PARAM_REVISION_ID_MAJREV_SHIFT)
3378 +#define HDA_PARAM_REVISION_ID_MINREV(param) \
3379 + (((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \
3380 + HDA_PARAM_REVISION_ID_MINREV_SHIFT)
3381 +#define HDA_PARAM_REVISION_ID_REVISION_ID(param) \
3382 + (((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \
3383 + HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT)
3384 +#define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \
3385 + (((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \
3386 + HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT)
3387 +
3388 +/* Subordinate Node Cound */
3389 +#define HDA_PARAM_SUB_NODE_COUNT 0x04
3390 +
3391 +#define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000
3392 +#define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16
3393 +#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff
3394 +#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0
3395 +
3396 +#define HDA_PARAM_SUB_NODE_COUNT_START(param) \
3397 + (((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \
3398 + HDA_PARAM_SUB_NODE_COUNT_START_SHIFT)
3399 +#define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \
3400 + (((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \
3401 + HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT)
3402 +
3403 +/* Function Group Type */
3404 +#define HDA_PARAM_FCT_GRP_TYPE 0x05
3405 +
3406 +#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100
3407 +#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8
3408 +#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff
3409 +#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0
3410 +
3411 +#define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \
3412 + (((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \
3413 + HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT)
3414 +#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \
3415 + (((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \
3416 + HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT)
3417 +
3418 +#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01
3419 +#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02
3420 +
3421 +/* Audio Function Group Capabilities */
3422 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08
3423 +
3424 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000
3425 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16
3426 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00
3427 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8
3428 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f
3429 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0
3430 +
3431 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \
3432 + (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \
3433 + HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT)
3434 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \
3435 + (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \
3436 + HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT)
3437 +#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \
3438 + (((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \
3439 + HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT)
3440 +
3441 +/* Audio Widget Capabilities */
3442 +#define HDA_PARAM_AUDIO_WIDGET_CAP 0x09
3443 +
3444 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000
3445 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20
3446 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000
3447 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16
3448 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000
3449 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT 13
3450 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000
3451 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT 12
3452 +#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800
3453 +#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11
3454 +#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400
3455 +#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10
3456 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200
3457 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9
3458 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100
3459 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8
3460 +#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080
3461 +#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7
3462 +#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040
3463 +#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6
3464 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020
3465 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5
3466 +#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010
3467 +#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4
3468 +#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008
3469 +#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3
3470 +#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004
3471 +#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2
3472 +#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002
3473 +#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1
3474 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001
3475 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0
3476 +
3477 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \
3478 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \
3479 + HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
3480 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \
3481 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \
3482 + HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT)
3483 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CC(param) \
3484 + ((((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK) >> \
3485 + (HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT - 1)) | \
3486 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
3487 + HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT))
3488 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \
3489 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK) >> \
3490 + HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT)
3491 +#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \
3492 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \
3493 + HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT)
3494 +#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \
3495 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \
3496 + HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT)
3497 +#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \
3498 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \
3499 + HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT)
3500 +#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \
3501 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \
3502 + HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT)
3503 +#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \
3504 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \
3505 + HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT)
3506 +#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \
3507 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \
3508 + HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT)
3509 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \
3510 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \
3511 + HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT)
3512 +#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \
3513 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \
3514 + HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT)
3515 +#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \
3516 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \
3517 + HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT)
3518 +#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \
3519 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \
3520 + HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT)
3521 +#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \
3522 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \
3523 + HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT)
3524 +#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \
3525 + (((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
3526 + HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)
3527 +
3528 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0
3529 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1
3530 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2
3531 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3
3532 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4
3533 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5
3534 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6
3535 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7
3536 +#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf
3537 +
3538 +/* Supported PCM Size, Rates */
3539 +
3540 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a
3541 +
3542 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000
3543 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20
3544 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000
3545 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19
3546 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000
3547 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18
3548 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000
3549 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17
3550 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000
3551 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16
3552 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001
3553 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0
3554 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002
3555 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1
3556 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004
3557 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2
3558 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008
3559 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3
3560 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010
3561 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4
3562 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020
3563 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5
3564 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040
3565 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6
3566 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080
3567 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7
3568 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100
3569 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8
3570 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200
3571 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9
3572 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400
3573 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10
3574 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800
3575 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11
3576 +
3577 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \
3578 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \
3579 + HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT)
3580 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \
3581 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \
3582 + HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT)
3583 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \
3584 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \
3585 + HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT)
3586 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \
3587 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \
3588 + HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT)
3589 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \
3590 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \
3591 + HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT)
3592 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \
3593 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \
3594 + HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT)
3595 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \
3596 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \
3597 + HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT)
3598 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \
3599 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \
3600 + HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT)
3601 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \
3602 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \
3603 + HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT)
3604 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \
3605 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \
3606 + HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT)
3607 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \
3608 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \
3609 + HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT)
3610 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \
3611 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \
3612 + HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT)
3613 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \
3614 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \
3615 + HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT)
3616 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \
3617 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \
3618 + HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT)
3619 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \
3620 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \
3621 + HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT)
3622 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \
3623 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \
3624 + HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT)
3625 +#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \
3626 + (((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \
3627 + HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT)
3628 +
3629 +/* Supported Stream Formats */
3630 +#define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b
3631 +
3632 +#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004
3633 +#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2
3634 +#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002
3635 +#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1
3636 +#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001
3637 +#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0
3638 +
3639 +#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \
3640 + (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \
3641 + HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT)
3642 +#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \
3643 + (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \
3644 + HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT)
3645 +#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \
3646 + (((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \
3647 + HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT)
3648 +
3649 +/* Pin Capabilities */
3650 +#define HDA_PARAM_PIN_CAP 0x0c
3651 +
3652 +#define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000
3653 +#define HDA_PARAM_PIN_CAP_HBR_SHIFT 27
3654 +#define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000
3655 +#define HDA_PARAM_PIN_CAP_DP_SHIFT 24
3656 +#define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000
3657 +#define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16
3658 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00
3659 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8
3660 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000
3661 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13
3662 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000
3663 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12
3664 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400
3665 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10
3666 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200
3667 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9
3668 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100
3669 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8
3670 +#define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080
3671 +#define HDA_PARAM_PIN_CAP_HDMI_SHIFT 7
3672 +#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040
3673 +#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6
3674 +#define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020
3675 +#define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5
3676 +#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010
3677 +#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4
3678 +#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008
3679 +#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3
3680 +#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004
3681 +#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2
3682 +#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002
3683 +#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1
3684 +#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001
3685 +#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0
3686 +
3687 +#define HDA_PARAM_PIN_CAP_HBR(param) \
3688 + (((param) & HDA_PARAM_PIN_CAP_HBR_MASK) >> \
3689 + HDA_PARAM_PIN_CAP_HBR_SHIFT)
3690 +#define HDA_PARAM_PIN_CAP_DP(param) \
3691 + (((param) & HDA_PARAM_PIN_CAP_DP_MASK) >> \
3692 + HDA_PARAM_PIN_CAP_DP_SHIFT)
3693 +#define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \
3694 + (((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \
3695 + HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT)
3696 +#define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \
3697 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \
3698 + HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT)
3699 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \
3700 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \
3701 + HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT)
3702 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \
3703 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \
3704 + HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT)
3705 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \
3706 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \
3707 + HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT)
3708 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \
3709 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \
3710 + HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT)
3711 +#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \
3712 + (((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \
3713 + HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT)
3714 +#define HDA_PARAM_PIN_CAP_HDMI(param) \
3715 + (((param) & HDA_PARAM_PIN_CAP_HDMI_MASK) >> \
3716 + HDA_PARAM_PIN_CAP_HDMI_SHIFT)
3717 +#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \
3718 + (((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \
3719 + HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT)
3720 +#define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \
3721 + (((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \
3722 + HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT)
3723 +#define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \
3724 + (((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \
3725 + HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT)
3726 +#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \
3727 + (((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \
3728 + HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT)
3729 +#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \
3730 + (((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \
3731 + HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT)
3732 +#define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \
3733 + (((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \
3734 + HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT)
3735 +#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \
3736 + (((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \
3737 + HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT)
3738 +
3739 +/* Input Amplifier Capabilities */
3740 +#define HDA_PARAM_INPUT_AMP_CAP 0x0d
3741 +
3742 +#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
3743 +#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31
3744 +#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
3745 +#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16
3746 +#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
3747 +#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8
3748 +#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f
3749 +#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0
3750 +
3751 +#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \
3752 + (((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \
3753 + HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT)
3754 +#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \
3755 + (((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \
3756 + HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT)
3757 +#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \
3758 + (((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \
3759 + HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT)
3760 +#define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \
3761 + (((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \
3762 + HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT)
3763 +
3764 +/* Output Amplifier Capabilities */
3765 +#define HDA_PARAM_OUTPUT_AMP_CAP 0x12
3766 +
3767 +#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
3768 +#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31
3769 +#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
3770 +#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16
3771 +#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
3772 +#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8
3773 +#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f
3774 +#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0
3775 +
3776 +#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \
3777 + (((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \
3778 + HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT)
3779 +#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \
3780 + (((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \
3781 + HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT)
3782 +#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \
3783 + (((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \
3784 + HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT)
3785 +#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \
3786 + (((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \
3787 + HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT)
3788 +
3789 +/* Connection List Length */
3790 +#define HDA_PARAM_CONN_LIST_LENGTH 0x0e
3791 +
3792 +#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080
3793 +#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7
3794 +#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f
3795 +#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0
3796 +
3797 +#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \
3798 + (((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \
3799 + HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT)
3800 +#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \
3801 + (((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \
3802 + HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT)
3803 +
3804 +/* Supported Power States */
3805 +#define HDA_PARAM_SUPP_POWER_STATES 0x0f
3806 +
3807 +#define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008
3808 +#define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3
3809 +#define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004
3810 +#define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2
3811 +#define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002
3812 +#define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1
3813 +#define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001
3814 +#define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0
3815 +
3816 +#define HDA_PARAM_SUPP_POWER_STATES_D3(param) \
3817 + (((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \
3818 + HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT)
3819 +#define HDA_PARAM_SUPP_POWER_STATES_D2(param) \
3820 + (((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \
3821 + HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT)
3822 +#define HDA_PARAM_SUPP_POWER_STATES_D1(param) \
3823 + (((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \
3824 + HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT)
3825 +#define HDA_PARAM_SUPP_POWER_STATES_D0(param) \
3826 + (((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \
3827 + HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT)
3828 +
3829 +/* Processing Capabilities */
3830 +#define HDA_PARAM_PROCESSING_CAP 0x10
3831 +
3832 +#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00
3833 +#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8
3834 +#define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001
3835 +#define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0
3836 +
3837 +#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \
3838 + (((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \
3839 + HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT)
3840 +#define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \
3841 + (((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \
3842 + HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT)
3843 +
3844 +/* GPIO Count */
3845 +#define HDA_PARAM_GPIO_COUNT 0x11
3846 +
3847 +#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000
3848 +#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31
3849 +#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000
3850 +#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30
3851 +#define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000
3852 +#define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16
3853 +#define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00
3854 +#define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8
3855 +#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff
3856 +#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0
3857 +
3858 +#define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \
3859 + (((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \
3860 + HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT)
3861 +#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \
3862 + (((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \
3863 + HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT)
3864 +#define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \
3865 + (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \
3866 + HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT)
3867 +#define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \
3868 + (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \
3869 + HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT)
3870 +#define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \
3871 + (((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \
3872 + HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT)
3873 +
3874 +/* Volume Knob Capabilities */
3875 +#define HDA_PARAM_VOLUME_KNOB_CAP 0x13
3876 +
3877 +#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080
3878 +#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7
3879 +#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f
3880 +#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0
3881 +
3882 +#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \
3883 + (((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \
3884 + HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT)
3885 +#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \
3886 + (((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \
3887 + HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT)
3888 +
3889 +
3890 +#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f
3891 +#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0
3892 +#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0
3893 +#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT 4
3894 +#define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00
3895 +#define HDA_CONFIG_DEFAULTCONF_MISC_SHIFT 8
3896 +#define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000
3897 +#define HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT 12
3898 +#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000
3899 +#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT 16
3900 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000
3901 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT 20
3902 +#define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000
3903 +#define HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT 24
3904 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000
3905 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT 30
3906 +
3907 +#define HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf) \
3908 + (((conf) & HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK) >> \
3909 + HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT)
3910 +#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf) \
3911 + (((conf) & HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) >> \
3912 + HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT)
3913 +#define HDA_CONFIG_DEFAULTCONF_MISC(conf) \
3914 + (((conf) & HDA_CONFIG_DEFAULTCONF_MISC_MASK) >> \
3915 + HDA_CONFIG_DEFAULTCONF_MISC_SHIFT)
3916 +#define HDA_CONFIG_DEFAULTCONF_COLOR(conf) \
3917 + (((conf) & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> \
3918 + HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
3919 +#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf) \
3920 + (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK) >> \
3921 + HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT)
3922 +#define HDA_CONFIG_DEFAULTCONF_DEVICE(conf) \
3923 + (((conf) & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> \
3924 + HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT)
3925 +#define HDA_CONFIG_DEFAULTCONF_LOCATION(conf) \
3926 + (((conf) & HDA_CONFIG_DEFAULTCONF_LOCATION_MASK) >> \
3927 + HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT)
3928 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf) \
3929 + (((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> \
3930 + HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT)
3931 +
3932 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30)
3933 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30)
3934 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30)
3935 +#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30)
3936 +
3937 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20)
3938 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20)
3939 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20)
3940 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20)
3941 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20)
3942 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20)
3943 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20)
3944 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20)
3945 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20)
3946 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20)
3947 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20)
3948 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20)
3949 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20)
3950 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20)
3951 +#define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20)
3952 +
3953 +#endif
3954
3955 Property changes on: hda_reg.h
3956 ___________________________________________________________________
3957 Added: svn:keywords
3958 + FreeBSD=%H
3959
3960 Index: hdac_reg.h
3961 ===================================================================
3962 --- hdac_reg.h (revision 0)
3963 +++ hdac_reg.h (revision 307412)
3964 @@ -0,0 +1,268 @@
3965 +/*-
3966 + * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3967 + * All rights reserved.
3968 + *
3969 + * Redistribution and use in source and binary forms, with or without
3970 + * modification, are permitted provided that the following conditions
3971 + * are met:
3972 + * 1. Redistributions of source code must retain the above copyright
3973 + * notice, this list of conditions and the following disclaimer.
3974 + * 2. Redistributions in binary form must reproduce the above copyright
3975 + * notice, this list of conditions and the following disclaimer in the
3976 + * documentation and/or other materials provided with the distribution.
3977 + *
3978 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
3979 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
3980 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
3981 + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
3982 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
3983 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
3984 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
3985 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
3986 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
3987 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
3988 + * SUCH DAMAGE.
3989 + *
3990 + * $FreeBSD$
3991 + */
3992 +
3993 +#ifndef _HDAC_REG_H_
3994 +#define _HDAC_REG_H_
3995 +
3996 +/****************************************************************************
3997 + * HDA Controller Register Set
3998 + ****************************************************************************/
3999 +#define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/
4000 +#define HDAC_VMIN 0x02 /* 1 - Minor Version */
4001 +#define HDAC_VMAJ 0x03 /* 1 - Major Version */
4002 +#define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */
4003 +#define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */
4004 +#define HDAC_GCTL 0x08 /* 4 - Global Control */
4005 +#define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */
4006 +#define HDAC_STATESTS 0x0e /* 2 - State Change Status */
4007 +#define HDAC_GSTS 0x10 /* 2 - Global Status */
4008 +#define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */
4009 +#define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */
4010 +#define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */
4011 +#define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */
4012 +#define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */
4013 +#define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */
4014 +#define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */
4015 +#define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */
4016 +#define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */
4017 +#define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */
4018 +#define HDAC_CORBCTL 0x4c /* 1 - CORB Control */
4019 +#define HDAC_CORBSTS 0x4d /* 1 - CORB Status */
4020 +#define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */
4021 +#define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */
4022 +#define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */
4023 +#define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */
4024 +#define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */
4025 +#define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */
4026 +#define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */
4027 +#define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */
4028 +#define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */
4029 +#define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */
4030 +#define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */
4031 +#define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */
4032 +#define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */
4033 +#define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */
4034 +#define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */
4035 +#define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */
4036 +#define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */
4037 +#define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */
4038 +#define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */
4039 +#define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */
4040 +#define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */
4041 +#define HDAC_SDFMT 0x92 /* 2 - fmt */
4042 +#define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */
4043 +#define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */
4044 +
4045 +#define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20))
4046 +#define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss))
4047 +#define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss))
4048 +#define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss))
4049 +#define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss))
4050 +#define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss))
4051 +#define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss))
4052 +#define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss))
4053 +#define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss))
4054 +#define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss))
4055 +
4056 +#define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20))
4057 +#define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss))
4058 +#define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss))
4059 +#define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss))
4060 +#define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss))
4061 +#define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss))
4062 +#define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss))
4063 +#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss))
4064 +#define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss))
4065 +#define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss))
4066 +
4067 +#define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))
4068 +#define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss))
4069 +#define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss))
4070 +#define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss))
4071 +#define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss))
4072 +#define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss))
4073 +#define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss))
4074 +#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss))
4075 +#define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss))
4076 +#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss))
4077 +
4078 +/****************************************************************************
4079 + * HDA Controller Register Fields
4080 + ****************************************************************************/
4081 +
4082 +/* GCAP - Global Capabilities */
4083 +#define HDAC_GCAP_64OK 0x0001
4084 +#define HDAC_GCAP_NSDO_MASK 0x0006
4085 +#define HDAC_GCAP_NSDO_SHIFT 1
4086 +#define HDAC_GCAP_BSS_MASK 0x00f8
4087 +#define HDAC_GCAP_BSS_SHIFT 3
4088 +#define HDAC_GCAP_ISS_MASK 0x0f00
4089 +#define HDAC_GCAP_ISS_SHIFT 8
4090 +#define HDAC_GCAP_OSS_MASK 0xf000
4091 +#define HDAC_GCAP_OSS_SHIFT 12
4092 +
4093 +#define HDAC_GCAP_NSDO_1SDO 0x00
4094 +#define HDAC_GCAP_NSDO_2SDO 0x02
4095 +#define HDAC_GCAP_NSDO_4SDO 0x04
4096 +
4097 +#define HDAC_GCAP_BSS(gcap) \
4098 + (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)
4099 +#define HDAC_GCAP_ISS(gcap) \
4100 + (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)
4101 +#define HDAC_GCAP_OSS(gcap) \
4102 + (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)
4103 +#define HDAC_GCAP_NSDO(gcap) \
4104 + (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT)
4105 +
4106 +/* GCTL - Global Control */
4107 +#define HDAC_GCTL_CRST 0x00000001
4108 +#define HDAC_GCTL_FCNTRL 0x00000002
4109 +#define HDAC_GCTL_UNSOL 0x00000100
4110 +
4111 +/* WAKEEN - Wake Enable */
4112 +#define HDAC_WAKEEN_SDIWEN_MASK 0x7fff
4113 +#define HDAC_WAKEEN_SDIWEN_SHIFT 0
4114 +
4115 +/* STATESTS - State Change Status */
4116 +#define HDAC_STATESTS_SDIWAKE_MASK 0x7fff
4117 +#define HDAC_STATESTS_SDIWAKE_SHIFT 0
4118 +
4119 +#define HDAC_STATESTS_SDIWAKE(statests, n) \
4120 + (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \
4121 + HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)
4122 +
4123 +/* GSTS - Global Status */
4124 +#define HDAC_GSTS_FSTS 0x0002
4125 +
4126 +/* INTCTL - Interrut Control */
4127 +#define HDAC_INTCTL_SIE_MASK 0x3fffffff
4128 +#define HDAC_INTCTL_SIE_SHIFT 0
4129 +#define HDAC_INTCTL_CIE 0x40000000
4130 +#define HDAC_INTCTL_GIE 0x80000000
4131 +
4132 +/* INTSTS - Interrupt Status */
4133 +#define HDAC_INTSTS_SIS_MASK 0x3fffffff
4134 +#define HDAC_INTSTS_SIS_SHIFT 0
4135 +#define HDAC_INTSTS_CIS 0x40000000
4136 +#define HDAC_INTSTS_GIS 0x80000000
4137 +
4138 +/* SSYNC - Stream Synchronization */
4139 +#define HDAC_SSYNC_SSYNC_MASK 0x3fffffff
4140 +#define HDAC_SSYNC_SSYNC_SHIFT 0
4141 +
4142 +/* CORBWP - CORB Write Pointer */
4143 +#define HDAC_CORBWP_CORBWP_MASK 0x00ff
4144 +#define HDAC_CORBWP_CORBWP_SHIFT 0
4145 +
4146 +/* CORBRP - CORB Read Pointer */
4147 +#define HDAC_CORBRP_CORBRP_MASK 0x00ff
4148 +#define HDAC_CORBRP_CORBRP_SHIFT 0
4149 +#define HDAC_CORBRP_CORBRPRST 0x8000
4150 +
4151 +/* CORBCTL - CORB Control */
4152 +#define HDAC_CORBCTL_CMEIE 0x01
4153 +#define HDAC_CORBCTL_CORBRUN 0x02
4154 +
4155 +/* CORBSTS - CORB Status */
4156 +#define HDAC_CORBSTS_CMEI 0x01
4157 +
4158 +/* CORBSIZE - CORB Size */
4159 +#define HDAC_CORBSIZE_CORBSIZE_MASK 0x03
4160 +#define HDAC_CORBSIZE_CORBSIZE_SHIFT 0
4161 +#define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0
4162 +#define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4
4163 +
4164 +#define HDAC_CORBSIZE_CORBSIZE_2 0x00
4165 +#define HDAC_CORBSIZE_CORBSIZE_16 0x01
4166 +#define HDAC_CORBSIZE_CORBSIZE_256 0x02
4167 +
4168 +#define HDAC_CORBSIZE_CORBSZCAP_2 0x10
4169 +#define HDAC_CORBSIZE_CORBSZCAP_16 0x20
4170 +#define HDAC_CORBSIZE_CORBSZCAP_256 0x40
4171 +
4172 +#define HDAC_CORBSIZE_CORBSIZE(corbsize) \
4173 + (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)
4174 +
4175 +/* RIRBWP - RIRB Write Pointer */
4176 +#define HDAC_RIRBWP_RIRBWP_MASK 0x00ff
4177 +#define HDAC_RIRBWP_RIRBWP_SHIFT 0
4178 +#define HDAC_RIRBWP_RIRBWPRST 0x8000
4179 +
4180 +/* RINTCTN - Response Interrupt Count */
4181 +#define HDAC_RINTCNT_MASK 0x00ff
4182 +#define HDAC_RINTCNT_SHIFT 0
4183 +
4184 +/* RIRBCTL - RIRB Control */
4185 +#define HDAC_RIRBCTL_RINTCTL 0x01
4186 +#define HDAC_RIRBCTL_RIRBDMAEN 0x02
4187 +#define HDAC_RIRBCTL_RIRBOIC 0x04
4188 +
4189 +/* RIRBSTS - RIRB Status */
4190 +#define HDAC_RIRBSTS_RINTFL 0x01
4191 +#define HDAC_RIRBSTS_RIRBOIS 0x04
4192 +
4193 +/* RIRBSIZE - RIRB Size */
4194 +#define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03
4195 +#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0
4196 +#define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0
4197 +#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4
4198 +
4199 +#define HDAC_RIRBSIZE_RIRBSIZE_2 0x00
4200 +#define HDAC_RIRBSIZE_RIRBSIZE_16 0x01
4201 +#define HDAC_RIRBSIZE_RIRBSIZE_256 0x02
4202 +
4203 +#define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10
4204 +#define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20
4205 +#define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40
4206 +
4207 +#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \
4208 + (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)
4209 +
4210 +/* DPLBASE - DMA Position Lower Base Address */
4211 +#define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80
4212 +#define HDAC_DPLBASE_DPLBASE_SHIFT 7
4213 +#define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001
4214 +
4215 +/* SDCTL - Stream Descriptor Control */
4216 +#define HDAC_SDCTL_SRST 0x000001
4217 +#define HDAC_SDCTL_RUN 0x000002
4218 +#define HDAC_SDCTL_IOCE 0x000004
4219 +#define HDAC_SDCTL_FEIE 0x000008
4220 +#define HDAC_SDCTL_DEIE 0x000010
4221 +#define HDAC_SDCTL2_STRIPE_MASK 0x03
4222 +#define HDAC_SDCTL2_STRIPE_SHIFT 0
4223 +#define HDAC_SDCTL2_TP 0x04
4224 +#define HDAC_SDCTL2_DIR 0x08
4225 +#define HDAC_SDCTL2_STRM_MASK 0xf0
4226 +#define HDAC_SDCTL2_STRM_SHIFT 4
4227 +
4228 +#define HDAC_SDSTS_DESE (1 << 4)
4229 +#define HDAC_SDSTS_FIFOE (1 << 3)
4230 +#define HDAC_SDSTS_BCIS (1 << 2)
4231 +
4232 +#endif
4233
4234 Property changes on: hdac_reg.h
4235 ___________________________________________________________________
4236 Added: svn:keywords
4237 + FreeBSD=%H
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