The AR9300 and later chipset support requires a new HAL and a bunch of infrastructure changes in the driver itself.
Ok, so how's it differ from the previous chipsets?
There's a few things from a programming perspective that have changed:
- MSI interrupts - which are optional and I haven't yet implemented;
- FIFO based DMA rather than list based DMA;
- TX completion status occurs in a single TX completion FIFO that the hardware writes to - previous chips glued the TX completion status at the end of a list of TX descriptors;
- RX occurs in two FIFOs - a high priority FIFO for frames like power save and uapsd frames, and a low priority FIFO for everything else;
- MCS16-23 support - ie, 3 stream operation;
- There's a new bluetooth coexistence method;
- 3 stream transmit can draw more power than the PCIe bus is rated for, so some smarts are needed when transmitting in order to keep the power draw in a manageable range;
- LDPC support;
- PA pre-distortion support for more accurate TX power calibration (not yet implemented)
Ok, so what is done so far?
Everything above (that isn't tagged as "not yet implemented"!) is done in the driver layer. The TX and RX paths need to be further optimised to handle the higher packet rates but that can come later.
What about the HAL?
The HAL is now open source.
The QCA release is here:
Adrian's fork for compiling in FreeBSD is here:
Check out the 'local/freebsd' branch when you clone Adrian's fork.
Ok, great. Now. How do I use this?
If you are running FreeBSD 10.0 or newer, It should "just work".
If you are running (a now unsupported) FreeBSD 9 you should know how to compile FreeBSD-HEAD's ath driver and wifi stack on -9. Please don't do this, and upgrade to a supported FreeBSD version.