Per-packet Transmission Power Control
| Driver | HAL | Supported Hardware |
What is it?
The AR5212, AR5416 and later (along with select previous generation devices) implement per-packet transmission power control.
Per-packet TPC is included for the AR5212 based chips, but needs to be verified before it can be enabled by default.
FreeBSD, Linux ath9k and Linux ath5k currently do not officially support per-packet TPC.
- AR_TPC controls the fixed ACK, CHIRP, CTS TX power level
- The descriptor contains a per-rate TX power level, passed to the baseband
- There's a register to flip on which controls per-packet TPC, rather than using the per-rate global TPC registers (documented in ath9k but not enabled)
What support is needed in the HAL?
- The TX power calibration code which calculates the per-rate TX power needs to be modified to store the per-rate information
- This needs to be then used for each packet to cap the TX power passed in by net80211 for the packet - since different TX rates have different TX power limits
- Need to keep in mind that various chipsets have different TX power configuration behaviour:
- AR5008, AR9001 series devices - 0.5dBm increments w/ 0 reflecting 0 dBm
- AR9002 series devices - 0.5dbm increments with 0 reflecting -5 dBm
- Maximum value is "63", so 31 dBm for AR5008/AR9001, 25 dBm for AR9002
- Open-loop TX power control on Merlin (and later, eg Kiwi?) need further tweaking for the CCK rates
- 20MHz versus 40MHz mode - there's a TX power change for that
- .. and does some tweaking need to occur for 5MHz/10MHz channels? That needs to be checked!
- What TX power levels should be configured for ACK, CTS, CHIRP? They are programmed at 0x3f (63) which is far too high; but then are capped by the global per-rate TX power registers
Which chips does it work on?
There's TPC support for the AR5212 but it hasn't been validated.
The TPC support for AR5416, AR9160, AR9280 have been validated in 2GHz. 5GHz should also just work. All of the above work is now done in code in ar5416/ar5416_xmit.c - it correctly offsets and clamps the TX power value before handing it to the hardware.
The TPC support for the AR9380 and later chips comes from the QCA HAL and thus it's assumed it just works.
- Writing a TX power value of '0' to the AR5416 TPC TX descriptor field causes a higher TX power to be used. Thus the lowest TX power value that can be set via TPC is 0.5dBm.