The page is dedicated to riscv "H"-extension[1].

The RISC-V Hypervisor specification virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor. Virtual machine implementations require the RISC-V Hypervisor specification. The Hypervisor specification will help drive RISC-V adoption in cloud and embedded applications where virtualization is critical, such as in data centers, automotive applications, and industrial control applications.

There is upcoming experimental support for bhyve on FreeBSD/riscv.

  1. https://github.com/riscv/riscv-isa-manual/blob/main/src/hypervisor.adoc

  2. https://five-embeddev.com/riscv-priv-isa-manual/Priv-v1.12/hypervisor.html

Code:

Project Status

Feature

Status

Notes

Owner

spike

supported

working in single-core

br

qemu

supported

working in single-core

br

VMID/ASID bits for stage 2

no support

TODO

MSI interrupts

no support

TODO

u-boot

unknown

PCIe emulation

supported

SMP in host

no support

SMP in guest

no support

multiple bhyve instances in host

unknown

bhyve SBI implementation ID

done

br

stage 2 pmap

done

br

check if APLIC emulation needs locking to protect structures

check if we want to trap rdcycle / rdtime and emulate it

Hardware

At the moment, no real hardware with H-extension implemented available.

Instructions

OpenSBI (host)

git clone https://github.com/riscv/opensbi.git

Reserve more space in opensbi memory layout for a large kernel if needed:

0 pie:/home/br/dev/opensbi %git diff
diff --git a/platform/generic/objects.mk b/platform/generic/objects.mk
index 85aa723..09b4330 100644
--- a/platform/generic/objects.mk
+++ b/platform/generic/objects.mk
@@ -32,7 +32,7 @@ else
   # This needs to be 2MB aligned for 64-bit system
   FW_JUMP_OFFSET=0x200000
 endif
-FW_JUMP_FDT_OFFSET=0x2200000
+FW_JUMP_FDT_OFFSET=0x4200000
 FW_PAYLOAD=y
 ifeq ($(PLATFORM_RISCV_XLEN), 32)
   # This needs to be 4MB aligned for 32-bit system

Spike

git clone https://github.com/riscv-software-src/riscv-isa-sim 
cd riscv-isa-sim
mkdir build && cd build
../configure
gmake

We currently rely on SSTC extension, so run Spike with sstc included. Use OpenSBI binary from previous step.

./spike -m4096 -d --isa RV64IMAFDCH_zicntr_zihpm_sstc --kernel /usr/obj/usr/home/br/dev/freebsd/riscv.riscv64/sys/GENERIC/kernel.bin ../../opensbi/build/platform/generic/firmware/fw_jump.elf

QEMU

git clone https://github.com/qemu/qemu
cd qemu
mkdir build && cd build
../configure --target-list=riscv64-softmmu
gmake -j `sysctl -n hw.ncpu`

./qemu-system-riscv64 -nographic \
        -machine virt \
        -cpu 'rv64,h=true' \
        -smp 1 \
        -m 8G \
        -bios ../../opensbi/build/platform/generic/firmware/fw_jump.elf \
        -kernel /usr/obj/usr/home/br/dev/freebsd/riscv.riscv64/sys/GENERIC/kernel.bin

Bhyve

Currently, we don't use any bootloader for the guest VM, instead the guest VM kernel binary (with rootfs included) is placed into memory using bootrom feature of bhyve(8).

The ahci-hd feature should also work instead of mdroot, but I didn't test.

The kernel.bin here is a generic freebsd kernel with no to little modifications (I'll update soon).

bhyve -m 2560 -o bootrom=/kernel.bin -o console=stdio -s 4,ahci-hd,/bin/ls test

riscv/bhyve (last edited 2024-06-20T12:47:14+0000 by RuslanBukin)