RISC-V

This page describes the status of the FreeBSD/RISC-V port, an adaptation of the FreeBSD Operating System to run on the RISC-V Instruction-Set Architecture (ISA). As a result of this work, FreeBSD is able to boot to multi-user mode on the Spike simulator and QEMU emulator. Following a number of commits to the FreeBSD subversion repository in January 2016 (see below), FreeBSD is the first operating system to have bootable in-tree support for RISC-V. This work was described in an EE Times article on the January 2016 RISC-V workshop. Next steps include multicore support, and the ability to boot on budding RISC-V SoCs such as Cambridge's lowRISC open-source SoC. This work was supported by the DARPA CTSRD Project at the University of Cambridge Computer Laboratory and is led by RuslanBukin.

The FreeBSD Foundation posted a blog article describing the RISC-V porting effort and merge of architectural support to the FreeBSD base system in January 2016.

Though RISC-V can support up to a 48-bit virtual addressing scheme, the FreeBSD/RISC-V port currently supports the 39-bit virtual addressing scheme (r298580).

Current status

Spike

fully supported

UP, SMP

Rocketchip

fully supported

UP

QEMU

fully supported

UP

lowRISC

not supported

Waiting for privileged v1.9 update (October 2016)

Source

Delivery into head:

Review

Commit

Description

D4445

r292124

kernel-toolchain

D4554

r292407

includes

D4679

r292691

rtld-elf

D4943

r294227

libc/libstand

D4982

r295041

kernel

D5014

r294571

xlint

D5020

r294573

jemalloc

D5021

r294577

compiler-rt

D5035

r294574

libunwind stubs

D5039

r294634

gcc config

D5040

r294662

libproc support

D5046

r294664

elftoolchain

D5048

r294665

usr.bin/ldd

D5064

r294908

libthread_db

D5063

r294912

libthr

D5178

r295253

reuse gp for pcpup

N/A

r295972

SMP support

N/A

r296614

DDB support

N/A

r303660

Privilege v1.9 update

N/A

r303908

Operation in machine mode removed

D8529

r308731

Full softfloat and hardfloat support

head build status: https://ci.freebsd.org/job/FreeBSD-head-riscv64-build/

People

RuslanBukin, ArunThomas, and EdMaste are doing the work. RobertWatson, AndrewTurner, DavidChisnall, and others are providing advice and moral support.

IRC channel

The related IRC channel related to this port is #freebsd-riscv in EFnet.

Toolchain

The only toolchain is supported at this moment is GNU one.

We would welcome efforts to improve RISC-V support in clang/LLVM, so we can switch. Clang/LLVM work is happening in the riscv-trunk branches of the RISC-V clang and LLVM repos:

https://github.com/riscv/riscv-clang/tree/riscv-trunk

https://github.com/riscv/riscv-llvm/tree/riscv-trunk

Sources

https://github.com/freebsd-riscv

Instructions

Setup toolchain installation directory

setenv PREFIX $HOME/riscv

Install required packages

sudo pkg install bison gmp mpfr mpc gawk gsed

Build Toolchain

git clone https://github.com/freebsd-riscv/riscv-gnu-toolchain
cd riscv-gnu-toolchain
git submodule update --init --recursive
./configure --prefix=$PREFIX
gmake -j16 freebsd

Alternatively, install devel/riscv64-xtoolchain-gcc, which gives you both devel/riscv64-binutils and devel/riscv64-gcc and a pre-defined riscv64-gcc.mk .

Build FreeBSD world

cd
svn co http://svn.freebsd.org/base/head freebsd-riscv
cd freebsd-riscv

When using toolchain built by hand:

setenv MAKEOBJDIRPREFIX /home/${USER}/obj/
setenv CROSS_BINUTILS_PREFIX $PREFIX/bin/riscv64-unknown-freebsd11.0-
setenv STRIPBIN ${CROSS_BINUTILS_PREFIX}strip
setenv XCC ${CROSS_BINUTILS_PREFIX}gcc
setenv XCXX ${CROSS_BINUTILS_PREFIX}c++
setenv XCPP ${CROSS_BINUTILS_PREFIX}cpp

setenv X_COMPILER_TYPE gcc
setenv WITHOUT_FORMAT_EXTENSIONS yes
setenv WITHOUT_NTP yes
setenv WITHOUT_SHAREDOCS yes

make TARGET_ARCH=riscv64 buildworld

When using devel/riscv64-xtoolchain-gcc:

setenv MAKEOBJDIRPREFIX /home/${USER}/obj/
setenv WITHOUT_FORMAT_EXTENSIONS yes
make CROSS_TOOLCHAIN=riscv64-gcc TARGET_ARCH=riscv64 buildworld

Build 32mb rootfs image

setenv DESTDIR /home/${USER}/riscv-world
make TARGET_ARCH=riscv64 -DNO_ROOT -DWITHOUT_TESTS DESTDIR=$DESTDIR installworld
make TARGET_ARCH=riscv64 -DNO_ROOT -DWITHOUT_TESTS DESTDIR=$DESTDIR distribution
fetch https://raw.githubusercontent.com/bukinr/riscv-tools/master/image/basic.files
tools/tools/makeroot/makeroot.sh -s 32m -f basic.files riscv.img $DESTDIR

Kernel config

Ensure you have correct path to riscv.img in your kernel config:

options         MD_ROOT                                                                                                
options         MD_ROOT_SIZE=32768      # 32MB ram disk                                                                
makeoptions     MFS_IMAGE=/path/to/riscv.img                                                                           
options         ROOTDEVNAME=\"ufs:/dev/md0\"  

Build FreeBSD kernel

for Spike:
make TARGET_ARCH=riscv64 KERNCONF=SPIKE buildkernel
for QEMU:
make TARGET_ARCH=riscv64 KERNCONF=QEMU buildkernel

When using devel/riscv64-xtoolchain-gcc, add CROSS_TOOLCHAIN=riscv64-gcc in make parameters.

Build bbl

You must build BBL in order to boot FreeBSD

git clone https://github.com/freebsd-riscv/riscv-pk
cd riscv-pk
mkdir build && cd build
setenv CFLAGS "-nostdlib"
../configure --host=riscv64-unknown-freebsd11.0 --with-payload=path_to_freebsd_kernel
gmake LIBS=''
unsetenv CFLAGS

Build Spike simulator

# Use clang on FreeBSD
setenv CXX c++
setenv PREFIX $HOME/riscv

git clone https://github.com/freebsd-riscv/riscv-fesvr
cd riscv-fesvr
mkdir build && cd build
../configure --prefix=$PREFIX
gmake install

git clone https://github.com/freebsd-riscv/riscv-isa-sim
cd riscv-isa-sim
mkdir build && cd build
../configure --prefix=$PREFIX --with-fesvr=$PREFIX
gmake install
#TODO: failed to compile, stick "-x c++-header" in the problematic command line

Or install emulators/riscv-isa-sim

Run Spike simulator

Note: we rely on FDT data built-in to the kernel, so by default we have to run spike with 2 cores. Amount of memory can be any because we use sbi_query_memory() machine call instead of FDT data at this moment.

./riscv-isa-sim/build/spike -m1024 -p2 /path/to/bbl

Run RocketChip

Create sdcard using 'Quick instructions' on https://github.com/ucb-bar/fpga-zynq, then copy bbl to sdcard (to the first msdos partition). Once you have booted linux from sdcard on Zedboard, then you can run FreeBSD/RISC-V:

./fesvr-zynq /mnt/boot/bbl

Build QEMU emulator

git clone https://github.com/riscv/riscv-qemu
cd riscv-qemu
git submodule update --init pixman
./configure --target-list=riscv64-softmmu --prefix=$PREFIX
gmake
gmake install

Or install emulators/qemu-riscv

Run QEMU emulator

$PREFIX/bin/qemu-system-riscv64 -m 2048M -kernel /path/to/bbl -nographic

TODO

Project

Comments

Generic kernel

Get device tree source (DTS) file from the hardware/bootloader

C++

We have C++ cross compiler, but we have no C++ runtime

Packages for toolchain

32-bit kernel

KDB

Needs update KDB disassember to new ISA (instruction format changed)

FPGA implementations

ROCKET works, we wait lowRISC for hardware update

QEMU user mode

Implement FreeBSD-bits in QEMU for user-mode emulation, required for cross-building ports

DTrace

SDT MD part missing for new SDT implementation by markj@

PMC

No counters available yet in hardware

busdma

The implementation of busdma(9)

Known issues

Issue

Comments

No known issues

FreeBSD/RISC-V workshop slides video

FreeBSD Foundation blog post on the RISC-V port

ELF handling for thread-local storage

riscv (last edited 2017-03-25 21:54:34 by RuslanBukin)